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SY89200U

Status: In Production

Features:

  • Three low-skew LVDS output banks with programmable ÷1, ÷2 and ÷4 divider options
  • Three independently programmable output banks
  • Accepts a clock frequency up to 1.5GHz
  • <900ps IN-to-OUT propagation delay
  • <150ps rise/fall time
  • <50ps bank-to-bank phase offset
  • Ultra-low jitter design:
  • <1psRMS random jitter
  • <10psPP total jitter (clock)
  • Patent-pending input termination and VT pin accepts DC- and AC-coupled inputs (CML, PECL, LVDS)
  • LVDS-compatible outputs
  • CMOS/TTL-compatible output enable (EN) and divider select control
  • 2.5V ±5% power supply
  • -40°C to +85°C temperature range
  • Available in 32-pin (5mm x 5mm) QFN package
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

The SY89200U is a 2.5V precision, high-speed, integrated clock divider and LVDS fanout buffer capable of handling clocks up to 1.5GHz. Optimized for communications applications, the three independently controlled output banks are phase matched and can be configured for pass through (÷1), ÷2 or ÷4 divider ratios.The differential input includes Micrel's unique, 3-pin input termination architecture that allows the user to interface to any differential signal path. The low-skew, low-jitter outputs are LVDS-compatible with extremely fast rise/fall times guaranteed to be less than 150ps.The EN (enable) input guarantees that the ÷1, ÷2 and ÷4 outputs will start from the same state without any runt pulse after an asynchronous master rest (MR) is asserted. This is accomplished by enabling the outputs after a four-clock delay to allow the counters to synchronize.The SY89200U is part of Micrel's Precision Edge® product family.

Additional Features
    • Three low-skew LVDS output banks with programmable ÷1, ÷2 and ÷4 divider options
    • Three independently programmable output banks
    • Guaranteed AC performance over temperature and voltage:
      • Accepts a clock frequency up to 1.5GHz
      • <900ps IN-to-OUT propagation delay
      • <150ps rise/fall time
      • <50ps bank-to-bank phase offset
    • Ultra-low jitter design:
      • <1psRMS random jitter
      • <10psPP total jitter (clock)
    • Patent-pending input termination and VT pin accepts DC- and AC-coupled inputs (CML, PECL, LVDS)
    • LVDS-compatible outputs
    • CMOS/TTL-compatible output enable (EN) and divider select control
    • 2.5V ±5% power supply
    • -40°C to +85°C temperature range
    • Available in 32-pin (5mm x 5mm) QFN package
Parametrics
Name
Value
Product Type
Divider
Description
1:8
Input
ANY
Output
LVDS
Supply Voltage
2.5
Max Freq (GHz)
1.5
Max Prop Delay (ps)
900
Icc (mA)
350
Max Within Device Skew (ps)
25
OE
False
RPE
False
FSI
False
Input Mux
False
Input EQ
False
Output Type
LVDS

Documents

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Data Sheet

04/30/2018
522KB

User Guides


Development tools data is currently unavailable.

RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Width
Solder Composition
JEDEC Indicator
RoHS
China EFUP
SY89200UMG
0.064100
0.230833
32
VQFN
5x5x0.9mm
NiPdAu
e4
SY89200UMG-TR
0.064100
0.214000
32
VQFN
5x5x0.9mm
NiPdAu
e4
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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