High-speed SHA-3 IP core provides versatile support of all variants of the SHA-3 hash function and related extendable-output function SHAKE as well as the SHA-3 derived function cSHAKE and its variants KMAC, TupleHash and ParallelHash (including their arbitrary-length output variants). SHA-3 and SHAKE are defined in the NIST (National Institute of Standards and Technology) standard FIPS PUB 202 and cSHAKE, KMAC, TupleHash and ParallelHash are specified in NIST Special Publication 800-185..
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Features and Benefits
- Optimized resource requirements:
- Requires 4-input Lookup Tables (4LUTs) or 1853 6- input 4LUTs with Microchip PolarFire®.
- Uses only some internal memory blocks in a typical Microchip® FPGA implementation.
- Performance:
- Achieves a high throughput up to several 10s of Gbpswith high maximum clock frequency.
- Algorithm Support:
- Supports SHA-3-224/256/384/512, SHAKE-128/256, and cSHAKE-128/256.
- Covers all algorithms defined in and also all algorithms included in are supported via cSHAKE
- Secure Architecture:
- Execution time is independent of the input values and, consequently, provides full protection against timing-based side-channel attacks.
- Standard Compliance:
- Fully compliant with FIPS 202 and SP 800-185 XIP3030C can be used as a part of numerous systems and protocols that require SHA-3 or its derivatives.
- Easy Integration :
- Pure RTL without hidden CPU or software components.
- Vendor agnostics FPGA/ASIC implementation.
Licensing Options
For additional information contact: sales@xiphera.com or visit Xiphera
Documentation
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