In this IP core, processor would not be needed at all. The endpoint 0 (default control endpoint) is managed by the IP Core itself. Hence, user does not have to bother regarding endpoint 0 management. For non-zero endpoint, there is a FIFO interface. User needs to manage this FIFO interface for a data transfer over non-zero endpoint via simple RTL coding.
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Features and Benefits
- Supports LS (1.5 Mbps), FS (12 Mbps) and HS (480 Mbps) modes.
- Supports Control, Bulk, Interrupt, and Isochronous transfers.
- Capable to support up to 31 endpoints (1 default control endpoint +15 IN/OUT endpoints).
- Implemented in Verilog RTL.
- Ready to use component.
Licensing Options
For additional information, visit SLS webpage or contact SLS through info@slscorp.com email.
Documentation
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| usb2-0_fifo_interface | Link |