We detect you are using an unsupported browser. For the best experience, please visit the site using Chrome, Firefox, Safari, or Edge. X
Maximize Your Experience: Reap the Personalized Advantages by Completing Your Profile to Its Fullest. Update Here
Stay in the loop with the latest from Microchip. Update your profile while you are at it. Update Here
Complete your profile to access more resources. Update Here

SEQ_CONTROLLER


Implementation of field oriented control (FOC) of AC motor needs an intelligent state machine (FSM)apart from the transformations and closed loop control. It is useful to have all the state transitionsmanaged in a single IP module. The Sequence Controller IP manages the starting, stopping, fault, and fault clear operations through FSM. It also manages the transition from closed-loop to open-loop and vice versa. It acts as a master block that controls all other IPs involved in FOC. The sequence controller triggers the Analog-to-Digital Converter (ADC) sampling and conversion, enables and disables the Pulse Width Modulation (PWM) based on the motor operating state and also enables and disables current and speed PI controllers.


Features and Benefits


  • Core Functionality :
    • Provides a high-speed synchronous serial communication controller.
    • Implements a specific serial protocol, often something like SDLC (Synchronous Data Link Control).
    • Can act as a master or slave in the communication protocol.
    • Manages the data flow, including framing, error checking, and addressing.
  • Performance :
    • Optimized for high-speed operation.
    • Designed to be a low-resource-utilization core.
    • Typically provides a high-level of autonomy to offload the host CPU.
  • Programmability and Control :
    • Features a set of accessible registers for configuration and status reporting.
    • Allows for run-time selection of operational modes (e.g., master/slave, data rate).
    • Reports errors, such as CRC failures or framing errors, to the host system.
  • Interface and Integration :
    • Utilizes standard interfaces like AMBA AXI or APB for communication with a host processor.
    • Provides separate clock domains for the communication protocol and the host interface, with robust clock domain crossing (CDC) logic.

Licensing Options


Encrypted RTL free with any Libero license 

Documentation


Title
Sequence Controller User Guide Download