The NAND flash controller is compatible with ONFI standard and is suitable for high data throughput, with configurable on-the-fly error detection and correction. The IP-Core has support for SLC memory and up to 8 LUN. It can be configured to use APB or AXILite for the configuration bus and AHB/AXI for the data bus (DMA), allowing maximum data rate with minimal CPU involvement. ECC are automatically inserted when writing and used for correction when reading. Metrics regarding ECC success and correctability are provided in the IP Core's registers so the software can validate memory integrity. Along with the IP-Core, a Linux driver is provided through which the user can mount common file-systems like UBIFS.
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Features and Benefits
- ONFI version: 2.1
- Configurable page and OOB size
- Configurable ECC algorithm
- Up to 50MHz
- Configurable timing delays for ONFI interface
Licensing Options
For additional information, contact at: sales@novo.space
Documentation
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