Low-voltage differential signaling (LVDS) is a high-speed, low-power, general-purpose interfacestandard. Also known as the ANSI/TIA/EIA-644 standard, LVDS was approved in March 1996. LVDS uses differential signaling with a nominal signal swing of 350 mV differential. The low signal swing decreases rise and fall times to achieve the maximum transmission rates specified in the LVDS standard. With LVDS, signal swing does not depend on the voltage of any specific supply. LVDS uses current mode drivers, which limit power consumption. The differential signals are immune to ±1 V common voltage noise.
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Features and Benefits
- High-speed, low-power differential signaling (~350 mV)
- .7:1 serialization/deserialization using Clock Conditioning Circuit (CCC)
- Receiver :
- 4 LVDS inputs → 7-bit parallel outputs with alignment signals
- Transmitter :
- 7-bit parallel inputs → serialized LVDS outputs + differential clock
- .Performance :
- Parallel clock up to 90 MHz
- Serial clock up to 315 MHz
- ~630 Mbps per LVDS channel
- Built-in training pattern & loopback support for testing.
- Resource usage (example on M2S150T): Receiver ~990 DFFs/590 LUTs; Transmitter ~190 DFFs/80 LUTs.
Licensing Options
Encrypted RTL free with any Libero License
Documentation
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| UG0645: Low Voltage Differential Signaling 7:1 User Guide | Download |