CoreTSN

CoreTSN is a Time-Sensitive Networking core for Ethernet endpoints that need deterministic Layer 2 communication in real-time systems. It exists to move time-critical traffic handling into FPGA logic, where packet classification, scheduling, filtering, and reliability functions can operate with predictable behavior. The core fits designs that must carry both urgent control streams and best-effort traffic across the same network without letting congestion or contention disrupt critical flows. It works with external time synchronization logic to align network behavior to a shared time base, enabling coordinated transmission across distributed nodes. Its architecture combines stream-aware queue assignment, time-aware gating, credit-based shaping, frame preemption, and per-stream policy enforcement. This allows designers to build converged Ethernet systems that preserve low jitter, bounded latency, and traffic isolation without depending on software intervention for every packet decision. The core also supports redundant delivery models through frame replication and duplicate elimination, which helps maintain operation through link disruptions. With integrated MAC switching, management access, and traffic statistics, it provides a practical foundation for embedded TSN endpoints that must connect processing, fabric, and network interfaces in a controlled data path. It delivers the greatest value in industrial automation, robotics, automotive networking, and other synchronized embedded control systems.