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ATmegaS128

Status: In Production

Features:

  • High-performance, low-power AVR 8-bit microcontroller with advanced RISC architecture
  • 32 × 8 General Purpose Working Registers + Peripheral Control Registers
  • Up to 8MIPS throughput at 8MHz
  • On-chip 2-cycle multiplier
  • 128KBytes of In-System Self-programmable Flash program memory, with 4KBytes EEPROM and 4KBytes Internal SRAM
  • Optional Boot Code Section with Independent Lock Bits In-System
  • Programming by On-chip Boot Program
  • True Read-While-Write Operation
  • SPI Interface for In-System Programming JTAG (IEEE std. 1149.1 Compliant) Interface
  • Boundary-scan Capabilities According to the JTAG Standard
  • Extensive On-chip Debug Support
  • 53 Programmable I/O Lines   –  64-lead Ceramic Quad Flat Package (CQFP64)   –  64-lead Thin Profile Plastic Quad Plat Package (TQFP64)
  • Temperature:  -55°C to +125°C Speed Grades
  • Radiation Tolerance:  No Single Event Latch-up below a LET threshold of 62.5 MeV/mg/cm2 @ 125°C; tested up to a total ionizing dose of 30 krads(Si) according to MIL-STD-883 Method 1019
  • ESD better than 2000V HBM / 750V CDM
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Overview
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Development Environment
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Device Overview

Summary

ATmegaS128 is the space market version of the popular Microchip AVR® ATmega128. The space qualified version of this part adds: Ceramic & hermetic package, extended temperature range -55C to 125C, extended qualification flow according to QML-V or QML-Q space grade flow.  Radiation performance for the ATmegaS128 are:  SEL LET > 62.5 MeV.cm2/mg lead to latch up immune, SEU LET > 3 MeV.cm2/mg and TID up to 30 Krad (Si).

Additional Features

High-performance, low-power AVR 8-bit microcontroller with advanced RISC architecture

32 × 8 General Purpose Working Registers + Peripheral Control Registers

Up to 8MIPS throughput at 8MHz

On-chip 2-cycle multiplier

128KBytes of In-System Self-programmable Flash program memory, with 4KBytes EEPROM and 4KBytes Internal SRAM

Optional Boot Code Section with Independent Lock Bits In-System

Programming by On-chip Boot Program

True Read-While-Write Operation

SPI Interface for In-System Programming JTAG (IEEE std. 1149.1 Compliant) Interface

Boundary-scan Capabilities According to the JTAG Standard

Extensive On-chip Debug Support

53 Programmable I/O Lines   –  64-lead Ceramic Quad Flat Package (CQFP64)   –  64-lead Thin Profile Plastic Quad Plat Package (TQFP64)

Temperature:  -55°C to +125°C Speed Grades

Radiation Tolerance:  No Single Event Latch-up below a LET threshold of 62.5 MeV/mg/cm2 @ 125°C; tested up to a total ionizing dose of 30 krads(Si) according to MIL-STD-883 Method 1019

ESD better than 2000V HBM / 750V CDM

Parametrics
Name
Value
Operating Voltage Range (Vcc)
3 to 3.6
SPI
1
CPU
Rad Tol 8-bit AVR
EEPROM (Bytes)
4096
External Bus Interface
1
Max I/O Pins
53
I/O Supply Class Max
3.6
I2C
1
I/O Supply Class Min
3
Debug Interface
JTAG
Output Compare Channels
2
OperatingVoltageMax
3.6
Temp# Range Range (deg C)
-55 to 125
Flash (kBytes)
128
ADC Channels
8
Self Program Memory
Yes
Analog Comparators
1
UART
2
Ext Interrupts
8
Input Capture Channels
2
PWM Channels
2
RTC
Counter
SRAM (kBytes)
4
Timers
4
Max# Operating Freq# (MHz)
8
MPU / MMU
no / no
Pin Count
64
ADC Speed (ksps)
15
Watchdog
Yes
ADC Resolution (bits)
10
32kHz RTC
Yes
Calibrated RC Oscillator
Yes

Documents

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Data Sheet

12/13/2017
4017KB

Application Notes

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Applications Source code

11/01/2009
84KB
09/01/2005
2KB
12/11/2016
2KB
05/01/2002
951B
12/11/2016
36KB
10/01/2004
1004B
06/01/2008
23KB
12/11/2016
95KB
12/11/2016
860KB
07/01/2013
86KB
12/11/2016
156KB
12/11/2016
156KB
06/01/2006
230KB
10/01/2005
81KB
12/11/2016
19KB
06/01/2006
137KB
10/01/2008
156KB
10/01/2008
162KB
02/01/2011
66KB

Brochures

02/21/2017
868KB
02/11/2019
3359KB

Product Document

Quality-Reliability-ISOs

Code Examples

Development Environment

  • Demo & Evaluation Boards
  • Application Examples
Demo & Evaluation Boards
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