Status: In Production
The KSZ9896 is a fully integrated layer 2, managed, six-port gigabit Ethernet switch with numerous advanced features. Five of the six ports incorporate 10/100/1000 Mbps PHYs. The sixth port has a MAC interface that can be configured as GMII, RGMII, MII or RMII.
Full register access is available by SPI or I2C interfaces, and by optional in-band management via any of the data ports. PHY register access is provided by a MIIM interface.
Security features include support for IEEE 802.1X port-based authentication and Access Control List (ACL) filtering.
An assortment of power-management features including
Energy-Efficient Ethernet (EEE) have been designed in to
satisfy energy efficient environments.
Microchip's complimentary and confidential LANCheck® online design review service is available for customers who have selected our products for their application design-in. The LANCheck online design review service is subject to Microchip's Program Terms and Conditions and requires a myMicrochip account.
Non-blocking wire-speed Ethernet switching fabric
Full-featured forwarding and filtering control, including Access Control List (ACL) filtering
IEEE802.1X support (Port-Based Network Access Control)
IEEE802.1Q VLAN supportfor 128 active VLAN groups and the full range of 4096 VLAN IDs
IEEE802.1p/Q tag insertion or removal on a per port basis and support for double-tagging
VLAN ID tag/untag options on per port basis
IEEE802.3x full-duplex flow control and half-duplex back pressure collision control
IGMPv1/v2/v3 snooping for multicast packet filtering
IPv6 multicast listener discovery (MLD) snooping
QoS/CoS packets prioritization support: 802.1p, DiffServ-based and re-mapping of 802.1p priority field per-port basis on four priority levels
IPv4/IPv6 QoS support
Programmable rate limiting at ingress and egress ports
Broadcast storm protection
Four priority queues with dynamic packet mapping for IEEE802.1p, IPv4 DIFFSERV, IPv6 TrafficClass
MAC filtering function to filter or forward unknown unicast, multicast and VLAN packets
Self-address filtering for implementing ring topologies
I2C Interface to access all registers
MII management (MIIM, MDC/MDIO 2 wire) interface to access all PHY registers per IEEE 802.3 specification
In-band management to access all registers via any of the six ports, strap enabled
I/O pin strapping facility to set certain register bits from I/O pins at reset time
Development tools data is currently unavailable.
For pricing and availability, contact Microchip Local Sales.