In-Flight Reconfiguration of Space Qualified FPGA Demonstration Application

Key Features

This demonstration presents a solution to reconfigure a Microchip space qualified FPGA (RTG4 or PolarFire) using a Microchip radiation hardened SAMRH71 microcontroller. 

Multiple reasons why it may be necessary to reprogram after integration: 

• Post-launch bug fix 
• Processing algo enhancement/fine tuning after satellite deployment 
• Adapt flight hardware to previously unknown target/mission/item of interest 
• Repurposing of functioning flight hardware after mission completion 

If in-flight reconfiguration should come as the last resort in case of a system error,  the reconfiguration in-flight offers a solution to provide an additional level of reliability to the application.

For this demonstration, the radiation hardened SAMRH71 microcontroller monitors the configuration of the FPGA and can be programmed to implement various backup actions according the safety strategy defined for the application.  The demonstration software project code is accessible from Microchip GitHub repository  : adg_fpga_reconfiguration

The SAMRH71, a radiation hardened 32-bit MCU processor is used as the key processing unit that features: 

• Core Arm Cortex-M7 running at 100 MHz 
  • 16 Kbytes of I-Cache and 16 Kbytes of D-Cache with Error Code Correction (ECC) 
  • Simple-precision and double-precision HW Floating Point Unit (FPU) 
  • Memory Protection Unit (MPU) with 16 zones 
  • DSP Instructions, Thumb®-2 Instruction Set 
  • Embedded Trace Module (ETM) with instruction trace stream, including Trace Port Interface Unit (TPIU) 
• Memories 
  • 128 Kbytes embedded Flash with built-in ECC (up to 2 errors correction) 
  • >1 Mbytes embedded SRAM for Tightly Coupled Memory (TCM) and Multiport system SRAM with built-in ECC (up to 1 error correction) 
  • Hardened External Memory Controller (HEMC) to address PROM, SRAM and SDRAM with variable data size (from 8 bits to 48 bits) 
    • Up to 2 GB of external memory accessible 
    • Built-in ECC, allowing the correction of up to 2 bits per 32 bits 
• Flexible IO peripherals

The RTG4 is a high performance radiation tolerant FPGA that features :

• Efficient four-input Look-Up Tables (LUTs) with carry chains for high system performance up to 300 MHz without SET filter 
  
• 209 blocks of dual-port 24.5 Kbits SRAM (Large SRAM) with 250 MHz synchronous performance (512 × 36, 1 Kbit × 18) 
• 462 DSP mathblocks with 18-bit × 18-bit input signed multiplication and 44-bit output accumulator.
• SEU-hardened registers eliminate the need for Triple-Module Redundancy (TMR) 

The RT PolarFire is a radiation tolerant FPGA that features 

• 481K logic elements consisting of a 4-input Look-Up Table (LUT) with a fractureable D-type flipflop 
  
• 20 Kbit dual- or two-port Large Static Random Access Memory (LSRAM) block with built-in Single Error Correct Double Error Detect (SECDED) 
• 64 × 12 two-port μRAM block implemented as an array of latches 
• 18 × 18 math block with a pre-adder, a 48-bit accumulator, and an optional 16 deep x 18 coefficient ROM 

In this demonstration,

• For ease of configuration, bitstreams in the format or DAT files are stored in an SD Card then copied to SDRAM prior to transfer. In a final application, we could imagine that the FPGA image would be stored in a radiation hardened memory attached to the SAMRH71 external memory controller. 
•  Two different bitstreams are loaded from the SD Card to the FPGA fabric via JTAG. The image selection is based on the button pressed on the SAMRH71F20-EK evaluation kit: 
  • PBO → Load the DAT file prefixed by “PB0_”
  • PB1 → Load the DAT file prefixed by “PB1_” 
• The SAMRH71F20-EK evaluation kit LEDs provide visual feedback of the loading process. 

Indicative performance for the reconfiguration duration (JTAG mode) : 

• RTG4: 3m30s 
• PolarFire: 2m40s