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Display_Controller

The Video and Electronics Standard Association (VESA) standard defines standard timing signals for interfacing witha display such as a monitor. The display controller generates display synchronization signals based on the VESA standard for various display resolutions. It generates the horizontal and vertical sync signals, the horizontal and vertical active signals, and the frame end and data enable signals. The display controller IP generates signals which enable to read frame buffers from the Double Data Rate (DDR) memory. This helps in synchronizing a video source, such as a camera, to the display device. Display controller IP supports enabling/disabling the video pipeline delay compensation logic within the IP. 


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Features and Benefits

  • Interface and Connectivity:
    • Supports AXI4-Lite for register configuration.
    • Supports AXI4-Stream for video data transfer.
    • The core can generate synchronization signals (HSYNC, VSYNC, DE) and provide 24-bit RGB pixel data.
  • Color Depth and Space:
    • Operates at 1 Pixel Per Clock and 4 Pixels Per Clock
    • Works with 8-bit per pixel resolution.
    • Outputs 24-bit RGB, with an external LUT for a color palette.
    • Supports various color depths including 18, 24, 30, 32, and 36 bits per pixel.
    • Can handle both RGB and YCbCr color spaces.
    • Compatible with both progressive and interlaced video methods
  • Memory Access:
    • Uses an external memory as a frame buffer for display data.
    • Supports configurable memory data bus widths (e.g., 32, 64, 128, or 256 bits).
    • Allows display data copying without CPU intervention.

Licensing Options

Encrypted RTL free with any Libero license 

Documentation

Title
Display Controller User Guide Download