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CoreRXIODBITALIGN

This CoreRxIODBitAlign training IP is used in IO gearing blocks. This IP is geared specifically for bitalignment independent of the data or protocol being used. The CoreRxIODBitAlign provides controls toadd or remove delay from the data path relative to the clock path.


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Features and Benefits

  • Supports Bit Alignment with different eye widths 1-7
  • Supports different Fabric DDR modes 2/4/3p5/5
  • Supports Skip, Restart / Hold mechanism
  • Supports MIPI training through LP signaling start of frame
  • Supports 256 Tap delays for bit alignment

    • Licensing Options

    Free with any Libero License

    Documentation

    Title
    CoreRxIODBitAlign v2.3 User Guide Download