Low-power, small form-factor Cu PHY with IEEE 802.3az Energy Efficient Ethernet (EEE), Wake-on-LAN (WoL), Synchronous Ethernet (SyncE), and Fast Link Failure 2.0 (FLF2) indication, with widest I/O LVCMOS support. The VSC8540-04 device, offered in a small 8 mm x 8 mm single-row QFN package, is designed for space-constrained 10BASE-TX and EtherCAT® applications. It features integrated line-side termination to conserve board space, lower EMI, and improve system performance. Additionally, integrated RGMII version 2.0 standard timing compliant compensation eliminates the need for on-board delay lines.
The device supports the industry’s widest range of LVCMOS levels for a parallel MAC interface including 1.5 V, 1.8 V, 2.5 V, and 3.3 V, as well as 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V support on the MDIO/MDC interface. It includes Microchip’s EcoEthernet™ 2.0 technology with Energy Efficient Ethernet and power saving features to reduce power based on link state and cable reach. It optimizes power consumption at all link operating speeds, and features Wake-on-LAN power management using magic packets. The device has a recovered clock output for Synchronous Ethernet applications. Programmable clock squelch control is included to inhibit undesirable clocks from propagating and to help prevent timing loops. VSC8540-04 also includes Fast Link Failure 2.0 indication for high availability networks. As in the original FLF feature on previous generation PHYs, FLF 2.0 indicator identifies the onset of a link failure in less than 1 ms typical (using the default values), which goes beyond the IEEE 802.3 standard requirement of 750 ms ±10 ms (link master). FLF2 goes beyond the previous FLF indicator by adjusting the programmable threshold for applications where indication of even a potential link drop must be known at the microsecond level (<10 μs).
Development tools data is currently unavailable.
For pricing and availability, contact Microchip Local Sales.