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SY89202U

Status: In Production

Features:

  • Three low-skew LVPECL output banks with programmable ÷1, ÷2 and ÷4 divider options
  • Three independently programmable output banks
  • >1.5GHz clock frequency (fMAX)
  • <930ps In-to-Out tpd
  • <220ps tr/tf
  • <1psRMS random jitter (RJ)
  • <10psPP total jitter (clock)
  • Internal input termination
  • Patent-pending input termination and VT pin accepts AC- and DC-coupled inputs (CML, PECL, LVDS)
  • 800mV LVPECL output swing
  • CMOS/TTL-compatible output enable (EN) and divider select control
  • Power supply 2.5V +5% or 3.3V +10%
  • -40°C to +85°C industrial temperature range
  • Available in 32-pin QFN package
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

The SY89202U is a precision, high-speed, integrated clock divider LVPECL fanout buffer capable of handling clocks up to 1.5GHz. Optimized for communications applications, the three independently controlled output banks are phase matched and can be configured for pass-through (÷1), ÷2 or ÷4 divide ratios.The differential input includes Micrel's unique, 3-pin input termination architecture that allows the user to interface to any AC- or DC-coupled signal as small as 100mV (200mVpp) without any level shifting or termination resistor networks in the signal path. The low skew, low jitter outputs are 800mV, 100k compatible LVPECL, with extremely fast rise/fall times guaranteed to be less than 220ps.The EN (enable) input guarantees that the ÷1, ÷2 and ÷4 outputs will start from the same state without any runt pulse after an asynchronous MR (master reset) is asserted. This is accomplished by enabling the outputs after a four-clock delay to allow the counters to synchronize.The SY89202U is part of Micrel's Precision Edge® product family.

Additional Features
    • Three low-skew LVPECL output banks with programmable ÷1, ÷2 and ÷4 divider options
    • Three independently programmable output banks
    • Guaranteed AC performance over temp and voltage:
      • >1.5GHz clock frequency (fMAX)
      • <930ps In-to-Out tpd
      • <220ps tr/tf
    • Ultra-low jitter design:
      • <1psRMS random jitter (RJ)
    • <10psPP total jitter (clock)
    • Internal input termination
    • Patent-pending input termination and VT pin accepts AC- and DC-coupled inputs (CML, PECL, LVDS)
    • 800mV LVPECL output swing
    • CMOS/TTL-compatible output enable (EN) and divider select control
    • Power supply 2.5V +5% or 3.3V +10%
    • -40°C to +85°C industrial temperature range
    • Available in 32-pin QFN package
Parametrics
Name
Value
Product Type
Divider
Description
1:8
Input
ANY
Output
LVPECL
Supply Voltage
2.5/3.3
Max Freq (GHz)
1.5
Max Prop Delay (ps)
930
Icc (mA)
125
Max Within Device Skew (ps)
25
OE
False
RPE
False
FSI
False
Input Mux
False
Input EQ
False
Output Type
LVPECL

Documents

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Data Sheet

04/30/2018
644KB

User Guides


Development tools data is currently unavailable.

RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Width
Solder Composition
JEDEC Indicator
RoHS
China EFUP
SY89202UMG-TR
0.064100
0.214000
32
VQFN
5x5x0.9mm
NiPdAu
e4
SY89202UMG
0.064100
0.230833
32
VQFN
5x5x0.9mm
NiPdAu
e4
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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