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SY88063CL

Status: In Production

Features:

  • Multi-rate operation from 1.0625Gbps to 12.5Gbps
  • Selectable digital offset correction for internal offset compensation in the high-speed data path
  • Wide differential input range (5mVPP to 1800mVPP)
  • 3mVPP to 30mVPP
  • 4dB typical electrical hysteresis
  • 75ns typical; 120ns maximum
  • Selectable LOS or SD status signal indicator
  • TTL-compatible JAM input with internal pull-up
  • Low-noise CML data inputs with integrated 50Ω termination impedance to internal reference VREF
  • 25ps typical rise/fall times
  • Wide range power supply: 3.3V ±10%
  • Industrial temperature range: -40°C to +85°C
  • Available in a tiny 3mm x 3mm QFN package
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

The SY88063CL limiting post amplifier is designed for use in fiber-optic receivers for multi-rate applications from 1.0625Gbps to 12.5Gbps.

The SY88063CL contains a high-bandwidth, high-sensitivity input stage with user-programmable, wide-range SD assert/LOS de-assert threshold levels, which enables optimized system reach. Typically, 4dB of electrical hysteresis is provided to minimize LOS or SD chattering caused by noisy input signals. A logic level control pin is provided to enable user selection of an open-collector, TTL-compatible LOS or SD status indication signal with an external 5kΩ to 10kΩ pull-up resistor.

The SY88063CL provides fast SD assert and LOS de-assert times over the entire differential input voltage range of 5mVPP to 1800mVPP.

The SY88063CL input stage also provides a user-selectable digital offset correction (DOC) function to automatically compensate for internal device offsets in the high-speed data path.

The SY88063CL provides integrated 50Ω input and output impedances to optimize the high-speed signal paths and reduce component count. A TTL-compatible JAM input is provided to enable a SQUELCH function by feeding back the LOS or SD signal. The JAM input disables only the post amplifier output.

The SY88063CL operates from a single +3.3V power supply, over temperatures ranging from –40°C to +85°C.

To request the datasheet, please email us at tcg_help@microchip.com

For product comparison, please consider: SY88083L

Additional Features
  • Multi-rate operation from 1.0625Gbps to 12.5Gbps
  • Selectable digital offset correction for internal offset compensation in the high-speed data path
  • Wide differential input range (5mVPP to 1800mVPP)
  • Wide SD de-assert or LOS assert threshold range
    • 3mVPP to 30mVPP
    • 4dB typical electrical hysteresis
  • Fast SD assert and LOS de-assert times
    • 75ns typical; 120ns maximum
  • Selectable LOS or SD status signal indicator
  • TTL-compatible JAM input with internal pull-up
  • Low-noise CML data inputs with integrated 50Ω termination impedance to internal reference VREF
  • Low-noise CML data outputs with integrated 50Ω termination impedance
    • 25ps typical rise/fall times
  • Wide range power supply: 3.3V ±10%
  • Industrial temperature range: -40°C to +85°C
  • Available in a tiny 3mm x 3mm QFN package
Parametrics
Name
Value
Part Type
Burst Mode, Continuous Mode
Data Rate Capability
12.5
Power Supply (V)
3.3
Data Input Type
CML/PECL
Data Output Type
CML
LOS/SD
SD/LOS (TTL)
LOS/SD Gain
1X
RC Time Constant
20X
Hysteresis Typ (dB)
4

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RoHS Information

Part Number
Device Weight
Shipping Weight
Lead Count
Package Type
Package Width
Solder Composition
JEDEC Indicator
RoHS
China EFUP
SY88063CLMG
0.021300
0.050000
16
VQFN
3x3x0.9mm
NiPdAu
e4
Rohs icon
efup china icon
SY88063CLMG-TR
0.021300
0.801700
16
VQFN
3x3x0.9mm
NiPdAu
e4
Rohs icon
efup china icon
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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