Microchip logo
  • All
  • Products
  • Documents
  • Applications Notes
product primary image

PM8545

Switchtec PSX Programmable 80xG3 PCIe Switch

Status: In Production

Features:

  • 80 lanes, 40 ports, 40 NTBs, and 20 virtual switch partitions
  • Flexible port bifurcation with no restrictions on configuring ports as either upstream or downstream
  • Integrated enclosure management processor and I/O interfaces, SDK, and a turn-key enclosure management solution
  • Error containment for surprise-plug and unplug to prevent system crashes
  • Advanced diagnostics and debug features to identify, diagnose and fix problems
  • SDK enables customer-differentiated solutions in areas such as error containment and surprise-plug
View More
Overview
Documents
Development Environment
RoHS Information
Add To Cart

Device Overview

Summary

The Switchtec PM8545 PSX PCIe Gen 3 Storage Switch is a programmable, high-reliability PCIe Base Specification 3.1-compliant switch supporting 80 lanes, 40 ports, 20 virtual switch partitions, 40 Non-Transparent Bridges (NTBs), and hot- and surprise-plug controllers for each port. The switch family also features advanced error containment, comprehensive diagnostics and debug capabilities, a wide breadth of I/O interfaces, and an integrated MIPS processor. PSX switches utilize a system-on-chip architecture that optionally enables customer-differentiated solutions through firmware customization and enhancements.

For product comparison, please consider: PM8546, PM8544, PM8543, PM8542, PM8541

Additional Features
  • 80 lanes, 40 ports, 40 NTBs, and 20 virtual switch partitions
  • Flexible port bifurcation with no restrictions on configuring ports as either upstream or downstream
  • Integrated enclosure management processor and I/O interfaces, SDK, and a turn-key enclosure management solution
  • Error containment for surprise-plug and unplug to prevent system crashes
  • Advanced diagnostics and debug features to identify, diagnose and fix problems
  • SDK enables customer-differentiated solutions in areas such as error containment and surprise-plug
  • Error Containment
    • Advanced Error Reporting (AER) on all ports
    • Downstream port containment (DPC) on all downstream ports
    • Completion timeout synthesis (CTS) to prevent an error state in an upstream host due to incomplete non-posted transactions
    • Upstream Error Containment (UEC), a programmable feature protecting errors from propagating upstream
    • Hot- plug controllers per port
    • GPIOs configurable for different cable/connector standards
  • PCIe Interfaces
    • Passive, managed, and optical cables
    • SFF-8644, SFF-8643, SFF-8639, OCuLink, and other connectors
  • Diagnostics and Debug
    • Transaction Layer Packet (TLP) generator for testing and debugging of links and error handling
    • Built-in PCIe analyzer with flexible triggering
    • Real-time eye capture
    • Any-to-any port mirroring for debug purposes
    • External loopback
    • Errors, statistics, performance, and TLP latency counters
  • Peripheral I/O Interfaces
    • Up to 11 two-wire interfaces (TWIs) with SMBus support
    • Up to 4 SFF-8485-compliant SGPIO ports
    • Up to 106 parallel GPIO pins
    • 10/100 Ethernet MAC port (MII/RMII)
    • 16-bit local bus interface with ECC protection
    • Up to 4 UARTs
    • JTAG and EJTAG interface
  • High-speed I/O
    • PCIe Gen 3 8 GT/s
    • Supports PCIe-compliant link training and manual PHY configuration
  • Chiplink Diagnostic Tools
    • Extensive debug, diagnostics, configuration, and analysis tools with an intuitive GUI
    • Access to configuration data, management capabilities, and signal integrity analysis tools (such as real-time eye capture)
    • Connects to device over in-band PCIe or sideband signals (UART, TWI, and EJTAG)
  • Evaluation Kit
    • PM5461-KIT—PSX/PFX 96/80/64xG3, 1-Slot, 16 HD Evaluation Kit
Parametrics
Name
Value
Lanes
80
Ports
40
NTBs
40
Hot Plug Controllers
6
Power Dissipation
29.3
Bandwidth
174

Documents

Jump to:

Supporting Collateral


Development tools data is currently unavailable.

RoHS Information

Part Number
Device Weight (g)
Shipping Weight (grams)
Lead Count
Package Type
Package Width
Solder Composition
JEDEC Indicator
RoHS
China EFUP
PM8545B-FEI
12.586200
18.380952
1311
BBGA
37.5x37.5x3.40mm
SAC305
e1
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

Buy from Microchip

Grid
View
Table
View
Filter:
Apply
Clear
Only show products with samples
Product
Leads
Package Type
Temp Range
Packing Media
5K Pricing
Buy