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PL138-48

Status: In Production

Features:

  • Four differential 2.5V/3.3V LVPECL output pairs
  • Output Frequency: ≤1GHz
  • Two selectable differential input pairs
  • LVPECL, LVCMOS, LVDS, HCSL, SSTL, LVHSTL, CML
  • Output Skew: 25ps (typ.)
  • Part-to-part skew: 140ps (typ.)
  • Propagation delay: 1.5ns (typ.)
  • Additive Jitter: <100fs (typ.)
  • Operating Supply Voltage: 2.375V ~ 3.63V
  • Operating temperature range from -40°C to 85°C
  • Package availability: 20-pin TSSOP
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

The PL138-48 family is a high performance low-cost 1:4 outputs Differential LVPECL fanout buffer.The family of Differential LVPECL buffers are designed to operate from a single power supply of 2.5V±5% or 3.3V±10%. The differential input pairs are designed to accept most standard input signal levels, using an appropriate resistor bias network, and produce a high quality set of outputs with the lowest possible skew on the outputs, which is guaranteed for part-to-part or lot-to lot skew.Designed to fit in a small form-factor package, PL138 family offers up to 1GHz of output operation with very low-power consumption, and lowest additive jitter of any comparable device. The Output Enable feature, when activated, allows the IC to consume less than 10µA of current.

Additional Features
    • Four differential 2.5V/3.3V LVPECL output pairs
    • Output Frequency: ≤1GHz
    • Two selectable differential input pairs
    • Translates any standard single-ended or differential input format to LVPECL output. It can accept the following standard input formats and more:
      • LVPECL, LVCMOS, LVDS, HCSL, SSTL, LVHSTL, CML
    • Output Skew: 25ps (typ.)
    • Part-to-part skew: 140ps (typ.)
    • Propagation delay: 1.5ns (typ.)
    • Additive Jitter: <100fs (typ.)
    • Operating Supply Voltage: 2.375V ~ 3.63V
    • Operating temperature range from -40°C to 85°C
    • Package availability: 20-pin TSSOP
Parametrics
Name
Value
Product Type
Fanout & Buffer and Drivers
Description
2:4 PECL buffer 50fs Typ, 100fs Max Additive Phase Jitter
Input
LVDS/LVPECL/LVHSTL/SSTL/HCSL/LVCMOS
Output
LVPECL
Supply Voltage
2.5/3.3
Max Freq (GHz)
1
Max Prop Delay (ps)
890
Icc (mA)
145
Max Within Device Skew (ps)
37
OE
True
RPE
False
FSI
False
Input Mux
True
Input EQ
False
Output Type
LVPECL

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RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Width
Solder Composition
JEDEC Indicator
RoHS
China EFUP
PL138-48OC
0.078000
0.175676
20
TSSOP
4.4mm
Matte Tin
e3
PL138-48OC-R
0.078000
0.200000
20
TSSOP
4.4mm
Matte Tin
e3
PL138-48OI
0.078000
0.175676
20
TSSOP
4.4mm
Matte Tin
e3
PL138-48OI-R
0.078000
0.200000
20
TSSOP
4.4mm
Matte Tin
e3
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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