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Optimizing MOSFET and IGBT Gate Current to Minimize dv/dt Induced Failures in SMPS Circuits

Title:
Optimizing MOSFET and IGBT Gate Current to Minimize dv/dt Induced Failures in SMPS Circuits
Name:
Optimizing MOSFET and IGBT Gate Current to Minimize dv/dt Induced Failures in SMPS Circuits
Date:
06/24/2020
Author:
mscc
 
Application Notes & Source Code
 Last Updated
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  Optimizing MOSFET and IGBT Gate Current to Minimize dv/dt Induced Failures in SMPS Circuits
  06/24/2020
  217KB
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