CoreXAUI

CoreXAUI is a high-performance 10 Gigabit Ethernet extended sublayer (XGXS) IP designed for PolarFire and PolarFire SoC FPGA devices. It enables high-speed Ethernet connectivity by interfacing with SerDes blocks operating in PCS mode using built-in 8b10b encoding, decoding, and comma alignment logic. The core supports both standard XAUI and Reduced XAUI (RXAUI) configurations, allowing designers to choose between four-lane or two-lane implementations to achieve a 10 Gbps data rate. XAUI mode uses four SerDes lanes operating at 3.125 GHz, while RXAUI mode uses two lanes at 6.25 GHz, providing flexibility in routing complexity and system optimization. CoreXAUI implements a 64-bit XGMII interface for transmit and receive paths, enabling reliable packet transfer between MAC and physical layers. The architecture includes key functional blocks such as transmit controllers, RX deskew logic, synchronization mechanisms, and FIFO buffers for clock domain crossing, ensuring data alignment and integrity. With IEEE 802.3 compliance and support for lane alignment and deskew, CoreXAUI is well suited for high-bandwidth networking applications requiring deterministic and reliable communication.