CoreSDR_AHB provides a high-performance interface to Single Data Rate (SDR) Synchronous DynamicRandom Access Memory (SDRAM) devices. CoreSDR_AHB accepts read and write commands usingthe Advanced High-performance Bus (AHB) slave interface and translates these requests to thecommand sequences required by SDRAM devices.
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Features and Benefits
- High performance, SDR controller for standard SDRAM chips and dual in-line memory modules(DIMMs)
- Synchronous interface, fully pipelined internal architecture
- Supports up to 1,024 MB of memory
- Bank management logic monitors status of up to 8 SDRAM banks
- Support for AHB slave interface
- Data access of 8, 16, or 32 bits are allowed by masters
Licensing Options
Free with any Libero License
Documentation
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| CoreSDR_AHB_HB.pdf | Download |