CoreResetP is a reset management IP designed to handle sequencing and control of reset signals across FPGA subsystems. It ensures proper initialization of critical components such as DDR controllers, SERDES interfaces, and processor subsystems in SmartFusion2 and IGLOO2 devices. The IP manages multiple reset sources, including power-on reset, fabric reset, and subsystem resets, and coordinates their release based on system readiness conditions. This ensures correct startup behavior and prevents timing-related issues during initialization. CoreResetP includes configurable parameters for peripheral usage, device voltage settings, SERDES configuration, and reset behavior. It also supports soft reset control, enabling dynamic reset assertion via software or control logic. The IP integrates seamlessly with CoreConfigP and system-level control logic, making it an essential component in reliable FPGA system bring-up and runtime control.
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Features and Benefits
- Reset Sequencing Engine
- Manages reset timing for DDR, SERDES, and MSS
- Ensures proper system initialization
- Multiple Reset Sources
- Power- on reset
- Fabric and external resets
- Configurable Behavior
- Peripheral usage configuration
- Voltage and timing settings
- Soft Reset Support
- Software-controlled reset triggers
Licensing Options
Free with any Libero license
Documentation
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| CoreResetP v7.1 Handbook | Download |