This CoreQSPI provides AHB system Interface and SPI interface to connect with the SPI memory devices. The control registers is used to configure the IP in different modes and the FIFO is used to buffer the data across clock domains.
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Features and Benefits
- Master SPI Data Rate with programmable SPI clock HCLK/2, HCLK/4, or HCLK/6 and maximum data rate as HCLK/2
- Transmit and Receive FIFO’s : 16 byte transmit FIFO depth and 32 byte receive FIFO depth
- SPI Protocol with Master operation, it supports Motorola SPI, Extended SPI operation (1, 2, and 4-bit) for example: QSPI operation (4-bit operation), BSPI operation (2-bit operation), XIP (execute in place) and three or four-byte SPI address. The Slave select operation in idle cycles configurable.
- Supports 8- bit frames directly with back-to-back frame operation supports >8-bit frames. It also supports up to 4 GB Transfer (2**32 bytes).
- Direct Mode -Allows a CPU to directly control SPI interface pins.
Licensing Options
Free with any Libero license
Documentation
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| CoreQSPI Handbook | Download |