Designing With SmartFusion^® 2 SoC FPGAs Course

This two-day course is for FPGA designers, embedded designers and firmware engineers who are designing with Microchip’s SmartFusion 2 SoC family of FPGAs. Understand the SmartFusion 2 FPGA architecture, including the Microcontroller Subsystem (MSS), FPGA fabric, software tools and design flows for implementing SmartFusion 2 FPGA designs. This course includes hands-on lab exercises targeting one of the included SmartFusion 2 FPGA kits to provide practical applications of the material presented. Students may attend one or both days of training.

This class is held at Microchip's facility located on North First Street in San Jose, CA. Students who are unable to travel to San Jose can attend remotely via the web.

• Develop an understanding of the SmartFusion 2 FPGA architecture
• Develop an understanding of the SmartFusion 2 FPGA design flow to quickly implement SmartFusion 2 FPGA applications

• Familiarity with the FPGA design flow and microprocessor (MPU) code development
• Familiarity with the PolarFire FPGA family
• Familiarity with the Libero® SoC Design Suite toolset

• Day 1: SmartFusion 2 FPGA Fabric
• FPGA fabric resources
• Math blocks
• Clocking and global resources
• SmartFusion 2 FPGA I/Os
• Math block design techniques
• Hands-on labs
• Day 2: SmartFusion 2 FPGA Microcontroller Subsystem (MSS)
• Arm® Cortex®-M3 MSS
• Instruction cache
• Debug features (SWV, ETM)
• SmartFusion 2 FPGA AHB bus matrix
• Peripherals
• SmartFusion 2 FPGA eSRAM and eNVM
• SmartFusion 2 FPGA DDR bridge
• SmartFusion 2 FPGA fabric interface
• System Builder/SmartDesign MSS configurator
• Firmware drivers and sample projects for SoftConsole, Keil and IAR toolchains
• Adding user logic in SmartFusion 2 FPGA designs
• Hands-on labs

Enroll for the course by completing the registration materials. Available dates are presented on the registration page.