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Clock and Data Distribution

Microchip offers one of the most extensive arrays of clock distribution product lines in the industry. Ranging from 2 to 22 outputs, they support differential (LVPECL, LVDS, HCSL, CML) and single-ended CMOS outputs, and have a maximum clock rate of 7.0 GHz and data rate of 10.7 Gbps, with very low additive jitter. Microchip’s clock distribution family consist of TCXO fanout buffers, crystal or reference input fanout buffers, signal translators, cross-point switches, high-performance clock dividers, receiver-buffer drivers, multiplexers, delay lines and logic gates.

Fan Out Buffers
  • 2 - 22 outputs offered
  • PECL/LVDS/HCSL/CMOS
  • Up to 7.0 GHz clock rate & 10.7 Gbps data rate
Drivers & Receivers
  • PECL/LVPECL/CML/LVDS
  • Up to 7.0 GHz clock rate & 10.7 Gbps data rate
Zero-Delay Buffers
  • High perf. low skew, low jitter
  • Distributes high speed and spread spectrum clocks
PCIe Buffers
  • Gen 1, 2, 3 compliant
  • 2 - 19 outputs
Dividers
  • Divide by 1, 2, 3, 4, 5, 8, 16
  • Multiple Output Banks
  • Single-Ended & Differential
  • PECL/LVPECL/CML/LVDS
Logic Translators
  • Clock or data rates up to 7 GHz
  • Conversion from single-ended to diff.
Multiplexers
  • Up to 16 input Max
  • PECL/LVPECL/CML/LVDS
  • Up to 7.0 GHz clock rate & 10.7 Gbps data rate
Crosspoint Switches
  • Single & Dual Channel
  • Up to 6 GHz clock rate & 10.7 Gbps data rate
  • CML/LVDS
Backplane & Cable
  • Pre-Emphasis and Equalization
  • Single-Ended & Differential
  • Up to 6.4Gbps CML Output
Skew Management
  • 2.2 - 13.2ns Programmable delay
  • 10ps delay increments
  • Fine Tune Control
  • Chip Cascading: extend delay
Registers, Flip-Flops
  • Up to 8-bit shift registers
  • D flip-flops: CML Output
Please email us at tcg_help@microchip.com for more information.