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dsPIC33CK256MP203

100 MHz Single-Core 16-bit DSC

Status: In Production

Features:

  • 3.0V to 3.6V, -40ºC to +150ºC, DC to 100 MIPS
  • 4 sets of interrupt context saving registers, including ACC and CPU status for fast interrupt handling
  • 8 independent PWM pairs (16 total outputs) with up to 250ps resolution
  • 3 12-bit 3.5 MSPS ADC Modules each with 2 dedicated SARs and 1 shared SAR cores (3 S&Hs)
  • 3 analog comparators (15ns) with dedicated 12-bit DACs with hardware slope compensation
  • Up to 3 op amps with internal connection to ADC Module
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Overview
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Development Environment
Similar Devices
RoHS Information
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Device Overview

Summary

Microchip’s dsPIC33CK family of digital signal controllers (DSCs) features a single 100 MIPS 16-bit dsPIC® DSC core with integrated DSP and enhanced on-chip peripherals. These DSCs enable the design of high-performance, precision motor control systems that are more energy efficient, quieter in operation and provide extended motor life. They can be used to control BLDC, PMSM, ACIM, SR and stepper motors. These DSCs are also ideal for switched mode power supplies such as AC/DC, DC/DC, UPS and PFC, providing high-precision digital control of Buck, Boost, Fly-Back, Half-Bridge, Full-Bridge, LLC and other power circuits to reach the highest possible energy efficiency.  These devices are also ideal for high-performance general-purpose and robust applications.

The dsPIC33CK product family has many features that help simplify functional safety certifications for ASIL-B and ASIL-C focused applications including: 
• Functional Safety Manual, FMEDA and Diagnostic Software available under NDA upon request to your local sales office
• Learn more about 16-bit Functional Safety capabilities including hardware, software, and supporting collateral

Additional Features
  • Operating Conditions
    • 3.0V to 3.6V, -40ºC to +150ºC, DC to 100 MIPS
  • dsPIC33CK DSC Core
    • Up to 256 KBytes of Program Flash with ECC and Live Update (dual-partition Flash)
    • Up to 24 KBytes of Data SRAM with Memory Built in Self-Test (MBIST)
    • Modified Harvard architecture with 16-bit data and 24-bit instructions
    • Code efficient (C and Assembly) CPU architecture designed for real-time applications
    • 16 16-bit working registers
    • 4 sets of interrupt context saving registers, including ACC and CPU status for fast interrupt handling
    • Single-cycle, mixed-sign 32-bit MUL
    • Fast 6-cycle hardware 32/16 and 16/16 DIV
    • Dual 40-bit fixed point Accumulators (ACC) for DSP operations
    • Single-cycle MAC/MPY with dual data fetch and result write-back
    • Zero overhead looping support
  • High-Speed PWM Module
    • 8 independent PWM pairs (16 total outputs) with up to 250ps resolution
    • Dead-time insertion for rising and falling edges and dead-time compensation support
    • Clock chopping for high-frequency operation
    • Fault and current limit inputs
    • Flexible trigger configuration for ADC triggering
  • Advanced Analog Features
    • 3 12-bit 3.5 MSPS ADC Modules each with 2 dedicated SARs and 1 shared SAR cores (3 S&Hs)
    • 12, 16, 19, 20 or 24 ADC input channels (depending on package)
    • 4 digital comparators for reducing CPU overhead
    • 4 oversampling filers up to 256x for increased resolution (up to 16-bits)
    • 3 analog comparators (15ns) with dedicated 12-bit DACs with hardware slope compensation
    • Up to 3 op amps with internal connection to ADC Module
  • Timer/Counters/Output Compare/Input Capture
    • 10 16-bit timer/counters (up to 4 32-bit)
    • 14 PWM or Output Compare (OC) outputs
    • 9 Input Captures (IC) pins or internal connections from the CLC or Comparator Modules
    • Peripheral Trigger Generator (PTG) for scheduling complex sequences
    • 2 Quadrature Encoder Interface (QEI) Modules for optical encoder support
  • Communication Interfaces
    • 3 UARTs (15 Mbps) with automated protocol handling for LIN/J2602, DMX and IrDA®
    • 3 4-wire SPI/I2S up to 40 MHz with dedicated pins
    • 3 I2C Modules (up to 1 Mbps) with SMBus support
    • 2 Single-Edge Nibble Transmission (SENT) Modules for sensor interfacing
    • 4 DMA channels supporting UART, SPI, ADC, IC, OC and Timer data transfers
  • Special Features
    • 4 Configurable Logic Cell (CLC) Modules with user defined logic gate circuits
    • Programmable Pin Select (PPS) for peripheral pin function mapping
    • Parallel Master Port (PMP) for external data expansion
    • On-chip temperature sensor with direct ADC Module connection
  • Clock and Power Management
    • On-chip 8 MHz Fast RC (FRC) and 32 kHz Low-Power RC (LPRC) oscillators
    • Programmable PLLs with external oscillator clock sources and Reference Clock Output (REFO)
    • Fail-Safe Clock Monitor (FSCM) with 8 MHz Back-up Fast RC (BFRC) oscillator
    • Low-Power management modes - Sleep, Idle and Doze
    • Integrated Power-on Reset (POR) and Brown-Out Reset (BOR)
  • Debugger Development Support
    • In-Circuit and in application programming and debug support (ICSP)
    • On-chip debug trace buffer and run-time watch with 3 complex and 5 simple breakpoints
    • IEEE 1149.2 (JTAG) boundary scan support
  • Safety Features
    • Dead-Man Timer (DMT) safety feature clocked by instruction fetches
    • Watch Dog Timer (WDT)
    • CodeGuard™ security for program FLASH
    • Programmable Cyclic Redundancy Check (CRC)
    • FLASH ECC Fault Injection testing feature
    • ICSP™ write inhibit
    • Class B Safety Library, IEC 60730
  • Functional Safety support (ISO26262)
    • ASIL-B & ASIL-C focused applications
    • FMEDA, Diagnostic Software and Functional Safety manual available under NDA upon request to your sales office
  • Functional Safety hardware features
    • Multiple redundant clock sources
    • I/O Port read-back
    • Analog peripherals redundancies
    • Windowed Watchdog Timer
    • RAM BIST
    • Hardware traps
    • SFR locks
    • Write protection
    • Shadow working registers
Parametrics
Name
Value
Architecture
16-bit
Max CPU Speed (MHz)
100
CPU Speed (MIPS/DMIPS)
100
Program Memory Size (KB)
256
Multiple Flash Panels
Yes
Error Correction Code Program Flash
Yes
SRAM (KB)
24
Direct Memory Access Channels
4
Temperature Range (C)
-40 to 150
Operating Voltage Range (V)
3 to 3.6
Pin Count
36
Comparators
3
Analog Peripherals
3-A/D 16x12-bit @ 3500(ksps) 3-D/A 1x12-bit
UART
3
SPI
3
I2C
3
Timers
10 x 16-bit 4 x 32-bit
Motor Control PWM Outputs
12
SMPS PWM Outputs
12
Input Capture
9
Max PWM outputs (including complementary)
26
Number of PWM Time Bases
15
Output Compare Channels
14
Class B Hardware
Yes
Quadrature Encoder Interface
2
Configurable Cell Logic
4
Peripheral Trigger Generator
Yes
Peripheral Pin Select / Pin Muxing
Yes
Supported in MPLAB Code Configurator
Yes

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  • Socket: AC164420   PartNo: DSPIC33CK256MP203 (36M5)
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RoHS Information

Part Number
Device Weight (g)
Shipping Weight (grams)
Lead Count
Package Type
Package Width
Solder Composition
JEDEC Indicator
RoHS
China EFUP
DSPIC33CK256MP203-E/M5
0.109589
36
UQFN
5x5x0.6mm
Matte Tin
e3
DSPIC33CK256MP203-H/M5
0.109589
36
UQFN
5x5x0.6mm
Matte Tin
e3
DSPIC33CK256MP203-I/M5
0.109589
36
UQFN
5x5x0.6mm
Matte Tin
e3
DSPIC33CK256MP203T-I/M5
0.219091
36
UQFN
5x5x0.6mm
Matte Tin
e3
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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