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ZL30159

1-Ch Low Cost Line Card Synchronizer

Status: In Production

Features:

  • Precision synthesizer generates any clock-rate from 1 Hz to 177.5 MHz with jitter below 1ps
  • Programmable digital PLL synchronize to any clock rate from 1 Hz (1 pps) to 750 MHz
  • Input reference configurable as single ended LVCMOS (up to 177.5 MHz) or differential LVPECL (up to 750 MHz)
  • Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates
  • Programmable Digital PLL loop filter: 30 mHz, 14 Hz, 28 Hz, 56 Hz, 112 Hz, 224 Hz, 448 Hz or 896 Hz
  • Two LVCMOS outputs —from 1 Hz (1 pps) to 177.5 MHz
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

The ZL30159 single PLL rate converter is part of Microchip's ClockCenter platform and can synchronize to any clock rate from 1 Hz (1pps) to 750 MHz. The conversion from 1pps is especially useful for GPS clock generation to 25MHz or 156.25MHz. The ZL30159 includes a high precision synthesizer that can generate any clock rate from 1Hz to 177.5 MHz with jitter below 1ps.

Additional Features
  • Precision synthesizer generates any clock-rate from 1 Hz to 177.5 MHz with jitter below 1ps
  • Programmable digital PLL synchronize to any clock rate from 1 Hz (1 pps) to 750 MHz
  • Input reference configurable as single ended LVCMOS (up to 177.5 MHz) or differential LVPECL (up to 750 MHz)
  • Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates
  • Programmable Digital PLL loop filter: 30 mHz, 14 Hz, 28 Hz, 56 Hz, 112 Hz, 224 Hz, 448 Hz or 896 Hz
  • Two LVCMOS outputs —from 1 Hz (1 pps) to 177.5 MHz
  • Operates from a single crystal resonator or clock oscillator
  • Customer defined default device configuration, including input/output frequencies, is available via OTP(One Time Programmable) memory
  • Dynamically configurable via SPI/I2C interface and volatile configuration registers
  • Applications
  • • General purpose clock rate translator
  • • GPS receiver clock synthesizer
Parametrics
Name
Value
Type
General Purpose
DPLLs or Paths
1
DPLL Bandwidth (Hz)
-
Inputs
1 XTAL, 1 D
CMOS Outputs
2
Low-Jitter Synthesizers
1
Typical Jitter (12kHz-20MHz) fs RMS
<1000
Diff InputFreq Range
1 Hz-750 MHz
Output Freq Range
1 Hz-177.5 MHz
NV Memory
-
NCO ppb
-
Align
-

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Data Sheets

  
869KB

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RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Dimension
Solder Composition
JEDEC Indicator
RoHS
China EFUP
ZL30159GGG2
0.313500
1.361539
64
LBGA
9x9x1.72mm
SAC305
e1
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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