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ZL30122

SONET/SDH Line Card System Synchronizer

Status: In Production

Features:

  • Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-253-CORE and ITU-T G.813
  • Internal APLL provides standard output clock frequencies up to 622.08 MHz with jitter < 3 ps RMS suitable for GR-253-CORE OC-12 and G.813 STM-16 interfaces
  • Programmable output synthesizer generates clock frequencies from any multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz
  • Provides 3 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

The ZL30122 SONET/SDH Line Card Synchronizer is a highly integrated device that provides timing and synchronization for network interface cards. The DPLL is capable of locking to one of three input references and provides a wide variety of synchronized output clocks and frame pulses.

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Additional Features
  • Typical Applications
    • AMCs for AdvancedTCATMSystems
    • Multi-Service Edge Switches or Routers
    • DSLAM Line Cards
    • WAN Line Cards
    • RNC/Mobile Switching Center Line Cards
    • ADM Line Cards
  • Features & Benefits
    • Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-253-CORE and ITU-T G.813
    • Internal APLL provides standard output clock frequencies up to 622.08 MHz with jitter < 3 ps RMS suitable for GR-253-CORE OC-12 and G.813 STM-16 interfaces
    • Programmable output synthesizer generates clock frequencies from any multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz
    • Provides 3 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz
    • Digital Phase Locked-Loop (DPLL) provides all the features necessary for generating SONET/SDH compliant clocks including automatic hitless reference switching, automatic mode selection (locked, free-run, holdover), and selectable loop bandwidth
    • Generates several styles of output frame pulses with selectable pulse width, polarity, and frequency
Parametrics
Name
Value
Type
SyncE
DPLL Bandwidth (Hz)
14Hz to 890Hz
Inputs
3+3
Diff Outputs
1
CMOS Outputs
4
Low-Jitter Synthesizers
1
General Purpose Synthsizers
1
Typical Jitter (12kHz-20MHz) fs RMS
3
Diff InputFreq Range
-
Output Freq Range
2kHz to 622.08MHz
NV Memory
-
NCO ppb
-
Align
-

Documents

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Data Sheets

  
259KB

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RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Dimension
Solder Composition
JEDEC Indicator
RoHS
China EFUP
ZL30122GGG2
0.313500
1.361539
64
LBGA
9x9x1.72mm
SAC305
e1
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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