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ZL30109

PDH/SDH System Synchronizer

Status: In Production

Features:

  • Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E
  • Supports ITU-T G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces
  • Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces
  • Simple hardware control interface
  • Accepts two input references and synchronizes to any combination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz inputs
  • Provides a range of clock outputs: 1.544 MHz, 2.048 MHz, 16.384 MHz, 19.44 MHz and either 4.096 MHz and 8.192 MHz or 32.768 MHz and 65.536 MHz
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

The ZL30109 DS1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for multi-trunk DS1 and E1 transmission equipment. The 19.44 MHz output makes the ZL30109 also suitable for SDH line card applications.

Additional Features
  • Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E
  • Supports ITU-T G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces
  • Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces
  • Simple hardware control interface
  • Accepts two input references and synchronizes to any combination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz inputs
  • Provides a range of clock outputs: 1.544 MHz, 2.048 MHz, 16.384 MHz, 19.44 MHz and either 4.096 MHz and 8.192 MHz or 32.768 MHz and 65.536 MHz
  • Provides 5 styles of 8 kHz framing pulses and a 2 kHz multi-frame pulse
  • Holdover frequency accuracy of 1.5 x 10-7
  • Lock, Holdover and selectable Out of Range indication
  • Selectable loop filter bandwidth of 1.8 Hz or 922 Hz
  • Less than 24 psrms intrinsic jitter on the 19.44 MHz output clock, compliant with OC-3 and STM-1 jitter specifications
  • Less than 0.6 nspp intrinsic jitter on all output clocks
  • External master clock source: clock oscillator or crystal
Parametrics
Name
Value
Type
PDH/SDH
DPLLs or Paths
1
DPLL Bandwidth (Hz)
1.8 Hz or 922 Hz
Inputs
2
CMOS Outputs
10
Typical Jitter (12kHz-20MHz) fs RMS
up to OC-3/ STM-1
Diff InputFreq Range
2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz
Output Freq Range
65.536 MHz
NV Memory
N/A
NCO ppb
N/A
Align
4

Documents

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Data Sheets

  
452KB

Development tools data is currently unavailable.

RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Dimension
Solder Composition
JEDEC Indicator
RoHS
China EFUP
ZL30109QDG1
0.286700
2.562500
64
TQFP
10x10x1mm
Matte Tin
e3
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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