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WP33C2A1EFEI-450B2

WP3

WinPath3 Network Processors

Status: In Production

Features:

  • 12 RISC processors and 64 concurrent hardware threads processing at up to 450 MHz
  • Dual multi-threaded MIPS 34Kc® cores at 650MHz with L1 and L2 caches
  • 3 level hierarchical shaper with 16K Flows with WRED accelerators
  • 16x GbE and Two 10GbE MACs
  • 14 multi-standard SERDES lanes
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

This third generation of WinPath® products builds upon hundreds of successful customer communications system deployments and leverages the broad set of supplied protocols developed for WinPath1 and WinPath2. These protocols include support for L2 and L3 termination (including Ethernet, ML-PPP, IMA, CES), PWE3 (for Ethernet, TDM, HDLC, ATM), Packet Network Synchronization (IEEE 1588v2, Synchronous Ethernet, adaptive and differential clock recovery), interworking (MPLS, IPv4/IPv6 Routing, VLAN-aware bridging), OAM (for Ethernet and ATM), QoS (policing, shaping, per-flow queuing, WRED) and many others.

WinPath3 integrates control plane and enhanced data plane processing components. Control plane processing is based on two high performance MIPS 34K multi-threaded processors.

Data plane processing uses new hardware accelerators for packet classification, hierarchical shaping, additional security standards and more which have been added to off-load common processing tasks. These accelerators are flexibly combined with Microsemi's field-proven, fully-programmable, high performance, multi-threaded WinComm multi-core data path processor subsystem. The available number of cores in WinComm has increased from six to twelve along with increases in operating speed.



Additional Features
  • 12 RISC processors and 64 concurrent hardware threads processing at up to 450 MHz
  • Dual multi-threaded MIPS 34Kc® cores at 650MHz with L1 and L2 caches
  • 3 level hierarchical shaper with 16K Flows with WRED accelerators
  • 16x GbE and Two 10GbE MACs
  • 14 multi-standard SERDES lanes
  • 16 TDI supporting T1/E1/T3/E3 or CT/MVIP bus
  • 2.5MB Internal memory; 3x 16-bit / 32-bit DDR3 interfaces
  • 31mm x 31mm 896 FCBGA with 1mm ball pitch

Documents

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Supporting Collateral


Development tools data is currently unavailable.

RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Dimension
Solder Composition
JEDEC Indicator
RoHS
China EFUP
WP3232M5NHEI-320B2
0.000000
0.000000
896
B2BGA
31x31x3.25mm
SAC305
e1
WP32C2M6NHEI-400B2
0.000000
0.000000
896
B2BGA
31x31x3.25mm
SAC305
e1
WP32C0W5NHEI-450B2
0.000000
0.000000
896
B2BGA
31x31x3.25mm
SAC305
e1
WP3232M6NFEI-320B2
0.000000
0.000000
896
B1BGA
31x31x2.70mm
SAC305
e1
WP32C2W3EFEI-320B2
0.000000
0.000000
896
B1BGA
31x31x2.70mm
SAC305
e1
WP32C2W6NFEI-400B2
0.000000
0.000000
896
B1BGA
31x31x2.70mm
SAC305
e1
WP3362D4NFEI-320B2
0.000000
0.000000
896
B1BGA
31x31x2.70mm
SAC305
e1
WP33C2A1EFEI-450B2
0.000000
0.000000
896
B1BGA
31x31x2.70mm
SAC305
e1
WP33C2D4NFEI-450B2
0.000000
0.000000
896
B1BGA
31x31x2.70mm
SAC305
e1
WP34C2R6NFEI450B2R
0.000000
0.000000
896
B1BGA
31x31x2.70mm
SAC305
e1
WP3232M5NELI-320B2
0.000000
0.000000
896
B1BGA
31x31x2.70mm
SAC305
e1
WP32C2M6NELI-450B2
0.000000
0.000000
896
B1BGA
31x31x2.70mm
SAC305
e1
WP34C2R4NFEI-400B2
0.000000
0.000000
896
B1BGA
31x31x2.70mm
SAC305
e1
WP34C2R6EFEI450B2R
0.000000
0.000000
896
B1BGA
31x31x2.70mm
SAC305
e1
WP32C2A4EFEI-400B2
0.000000
0.000000
896
B1BGA
31x31x2.70mm
SAC305
e1
WP3392D4NFEI-320B2
0.000000
0.000000
896
B1BGA
31x31x2.70mm
SAC305
e1
WP34C2R4EFEI-400B2
0.000000
0.000000
896
B1BGA
31x31x2.70mm
SAC305
e1
WP32C2M6NELI-400B2
0.000000
0.000000
896
B1BGA
31x31x2.70mm
SAC305
e1
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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