Status: End of Life
The HV632 is a 32-channel gray-shade column driver IC designed for driving electrofluorescent displays. Using unique HVCMOS® technology, it is capable of 256 levels of gray shading by PWM conversion. Input data, in groups of eight, is latched into a set of data latches on both edges of the shift clock. The data shifted in the first data latch corresponds to HVOUT1, the second data latch corresponds to HVOUT2, and so on. These data are compared to the contents of the master binary counter which counts on both edges of the count clock. Each time the master counter begins to decrement from 1111 1111, the data in the data latches are compared with the contents of the counter; if they match, the corresponding outputs will go high. The master counter counts down to 00000001 and then starts to count up again. The outputs that are at high will stay at high until the contents of the counter match the data in the data latches again. Therefore, the higher the binary data in the data latches, the longer the outputs will stay at high. Thus, different high voltage pulse widths are produced. When the counter reaches its 1111 1111 count while counting up, the device is ready for the next operation cycle. A data value of 0000 0000 produces no pulse; the output stays low. The BLANK input signal will reset the master counter to all ones (1111 1111) and set all high voltage outputs to low, or will set all high voltage outputs to high state, when the POL is low. The POL input signal, forced low, will invert the polarity of the output pulse. If left unconnected, POL input will be pulled high to VDD by an on-chip resistor.
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