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ATSAMA5D27C-LD1G

LPDDR2 SiP 1Gbit

Status: In Production

Features:

  • ARM Cortex-A5 core: Up to 500 MHz, ARMv7-A architecture, ARM TrustZone, NEON™ Media Processing Engine, 8 Kbyte Embedded Trace Buffer (ETB)
  • Up to 500 MHz, ARMv7-A architecture, ARM TrustZone, NEON™ Media Processing Engine, 8 Kbyte Embedded Trace Buffer (ETB)
  • Memory Management Unit
  • 32-Kbyte L1 data cache, 32-Kbyte L1 instruction cache
  • 128-Kbyte L2 cache configurable to be used as an internal SRAM
  • 1Gb LPDDR2-SDRAM
  • One 128-Kbyte scrambled internal SRAM
  • One 160-Kbyte internal ROM, 64-Kbyte scrambled and maskable ROM embedding boot loader/Secure boot loader, 96-Kbyte unscrambled, unmaskable ROM for NAND Flash BCH ECC table
  • High-bandwidth scramblable 16-bit Double Data Rate (DDR) multiport dynamic RAM controller supporting the internal DDR2-SDRAM, including the “on-the-fly” encryption/decryption path
  • Low-Power Modes Ultra Low-power mode with fast wakeup capability Low-power Backup mode with 5-Kbyte SRAM and Sleep Walking™ features, Wakeup from up to nine wakeup pins, UART reception, analog comparison, Fast wakeup capability, Extended Backup mode with DDR2-SDRAM in Self-Refresh mode
  • Ultra Low-power mode with fast wakeup capability
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

The SAMA5D27C-LD1G System in Package (SiP) integrates the ARM® Cortex®-A5 processor-based SAMA5D27C MPU with 1 Gbit (128 Mbytes) of LPDDR2-SDRAM in a single package.  By combining the high-performance, ultra-low-power SAMA5D2 with LPDDR2-SDRAM in a single package, PCB routing complexity, area and number of layers is reduced in the majority of cases.  This makes board design easier and more robust by facilitating design for EMI, ESD and signal integrity.  This SiP targets applications using Linux OS and is available in a BGA361 package.

Additional Features
  • ARM Cortex-A5 core: Up to 500 MHz, ARMv7-A architecture, ARM TrustZone, NEON™ Media Processing Engine, 8 Kbyte Embedded Trace Buffer (ETB)
  • Up to 500 MHz, ARMv7-A architecture, ARM TrustZone, NEON™ Media Processing Engine, 8 Kbyte Embedded Trace Buffer (ETB)
  • Memory Management Unit
  • 32-Kbyte L1 data cache, 32-Kbyte L1 instruction cache
  • 128-Kbyte L2 cache configurable to be used as an internal SRAM
  • 1Gb LPDDR2-SDRAM
  • One 128-Kbyte scrambled internal SRAM
  • One 160-Kbyte internal ROM, 64-Kbyte scrambled and maskable ROM embedding boot loader/Secure boot loader, 96-Kbyte unscrambled, unmaskable ROM for NAND Flash BCH ECC table
  • High-bandwidth scramblable 16-bit Double Data Rate (DDR) multiport dynamic RAM controller supporting the internal DDR2-SDRAM, including the “on-the-fly” encryption/decryption path
  • 8-bit SLC/MLC NAND controller, with up to 32-bit Error Correcting Code (PMECC)
  • Low-Power Modes Ultra Low-power mode with fast wakeup capability Low-power Backup mode with 5-Kbyte SRAM and Sleep Walking™ features, Wakeup from up to nine wakeup pins, UART reception, analog comparison, Fast wakeup capability, Extended Backup mode with DDR2-SDRAM in Self-Refresh mode
  • Ultra Low-power mode with fast wakeup capability
  • Low-power Backup mode with 5-Kbyte SRAM and Sleep Walking™ features, Wakeup from up to nine wakeup pins, UART reception, analog comparison, Fast wakeup capability, Extended Backup mode with DDR2-SDRAM in Self-Refresh mode
  • LCD TFT controller up to 1024x768, with four overlays, rotation, post-processing and alpha blending, 24-bit parallel RGB
  • ITU-R BT. 601/656/1120 Image Sensor Controller (ISC) supporting up to 5 M-pixel sensors with a parallel 12-bit interface for Raw Bayer, YCbCr, Monochrome and JPEG-compressed sensor interface
  • Two Synchronous Serial Controllers (SSC), two Inter-IC Sound Controllers (I2SC), and one Stereo Class D amplifier
  • One Peripheral Touch Controller (PTC) with up to 8 X-lines and 8 Y-lines (64-channel capacitive touch)
  • One Pulse Density Modulation Interface Controller (PDMIC)
  • One USB high-speed device port (UDPHS) and one USB high-speed host port or two USB high-speed host ports (UHPHS)
  • One 10/100 Ethernet MAC (GMAC) Energy efficiency support (IEEE 802.3az standard), Ethernet AVB support with IEEE802.1AS time stamping, IEEE802.1Qav credit-based traffic-shaping hardware support, IEEE1588 Precision Time Protocol (PTP)
  • Energy efficiency support (IEEE 802.3az standard), Ethernet AVB support with IEEE802.1AS time stamping, IEEE802.1Qav credit-based traffic-shaping hardware support, IEEE1588 Precision Time Protocol (PTP)
  • Two high-speed memory card hosts: SDMMC0: SD 3.0, eMMC 4.51, 8 bits SDMMC1: SD 2.0, eMMC 4.41, 4 bits only
  • SDMMC0: SD 3.0, eMMC 4.51, 8 bits
  • SDMMC1: SD 2.0, eMMC 4.41, 4 bits only
  • Many other serial, timer and A/D modules
  • Up to 128 I/Os
  • Safety and Security: Integrity Check Monitor based on SHA256, Crypto engine (SHA512, AES256, TDES), TRNG, tamper pins, Secure Boot Loader, Programmable fuse box, On-the-fly AES encryption/decryption on DDR2-SDRAM and QSPI, 5 Kbytes of internal scrambled SRAM, 256 bits of scrambled and erasable registers, Active Die Shield, Environmental Monitors, Independent watchdog, Main crystal clock failure detector
  • Integrity Check Monitor based on SHA256, Crypto engine (SHA512, AES256, TDES), TRNG, tamper pins, Secure Boot Loader, Programmable fuse box, On-the-fly AES encryption/decryption on DDR2-SDRAM and QSPI, 5 Kbytes of internal scrambled SRAM, 256 bits of scrambled and erasable registers, Active Die Shield, Environmental Monitors, Independent watchdog, Main crystal clock failure detector
Parametrics
Name
Value
Part Family
SAMA5D2
Core
Cortex-A5
FPU
Yes
ARM Neon
Yes
Arm Trust Zone®
Yes
Max CPU Speed (MHz)
500
Core Voltage Range (V)
1.1 to 1.32
Vbat/Vddbu battery backup
Yes
Internal Oscillator
32kHz, 12MHz
SRAM (KB)
128
L1 Cache Memory (Instructions) (KB)
32
L1 Cache Memory (Data) (KB)
32
L2 Cache Memory (KB)
128
DRAM Bus Size (Bits)
16
Internal DRAM Type
LPDDR2
Internal DRAM Amount (MB)
128
NAND Interface
Yes
ECC Bits on NAND Interface
32
Number of EBIs
1
SDIO/SD-CARD/eMMC
2
QSPI
2
Direct Memory Access Channels
51
Max I/O Pins
128
Pincount
361
UART
10
ISO 7816
10
SPI
7
I2C
7
SSC
2
CAN
2
Type of CAN Module
CAN
LIN
Yes
USB Device and Host Ports
1 HS
USB Host Only Ports
1 HS & 1 HSIC
10/100 Ethernet MAC
1
Ethernet PTP & AVB Support
Ethernet PTP
Graphics Controller/GPU
Yes
Graphic LCD
24-bit
Hardware Touch Peripheral
PTC
Camera Interface
Yes
Integrity Check Monitor (ICM)
Yes
Secure Bootloader
Yes
Crypto Engine
Yes
External Memory Encrypt/Decrypt
Yes
Anti-Tamper Pins
8
Secure Key Storage (Fuse bits)
544
ADC Input
12
Max ADC Resolution (bits)
12
Max ADC Sampling Rate (ksps)
1000
Temp Sensor
Yes
Hardware RTCC/RTC
Yes
Watch Dog Timer
Yes
Max 16-Bit Digital Timers
4
Max 32-Bit Digital Timers
6
Input Capture
6
Standalone Output Compare/Standard PWM
6
Quadrature Encoder Interface
2
Temperature Range (C)
-40 to 85

Documents

Jump to:

Board Design Files

BSDL Files

02/11/2019
45KB

Brochures

03/14/2018
2472KB
12/10/2016
371KB

Product Document

IBIS

02/11/2019
7200KB

Software

06/21/2018
20121KB
06/21/2018
9295KB

User Guides


Development tools data is currently unavailable.

RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Width
Solder Composition
JEDEC Indicator
RoHS
China EFUP
ATSAMA5D27C-LD1G-CUR
0.488000
361
TFBGA
16x16x1.2mm
SAC105
e8
ATSAMA5D27C-LD1G-CU
2.059524
361
TFBGA
16x16x1.2mm
SAC105
e8
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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