Transport Layer Security (TLS) is a cryptographic protocol used for building a secure connection between a client and a server over the Internet. A hardware-based TLS 1.3 implementation enables high-level security in mission-critical industries, ensuring that security-critical operations are entirely self-reliant on hardware, eliminating the need for software. Despite the extensive feature set, Xiphera TLS 1.3 IP cores maintain a compact footprint, making them exceptionally well-suited for high-volume applications.
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TLS 1.3
Features and Benefits
- Optimised Performance:
- Despite its small size, TLS 1.3 Client IP core can support bulk traffic encryption and decryption speeds in excess of 1 Gbps.
- Follows RFC 8446 with selected ciphers Powered by AES256-GCM Cryptographic operations performed directly in hardware for security and performance Hardware-based key management Easy system
- Short Session Establishment Time:
- The FPGA-dependent execution time of the TLS1.3 handshake calculations is less than 100 ms at 100MHz clock.
- The FPGA execution time is constant and does not depend on the key values, thus providing protection against timing-based side-channel attacks.
- Hardware-based Security:
- The primary design goal of TLS 1.3 Client IP core is to avoid the potential weaknesses in software-based security, including but not limited to dependence on operating system security, vulnerabilities in third party cryptographic software libraries, and bugs in underlying processor architectures
- Hardware-based Cryptographic Operations:
- All the cryptographic mathematical operations are performed entirely in the FPGA, providing a substantial security and performance advantages compared to software-based TLS implementations
- Hardware-based Key Management:
- All the cryptographic keys are stored in dedicated internal FPGA memory, which provides a substantial security advantage over software-based key management, and amongst other benefits is a requirement for IEC62443 Security Level 3 designs.
- Easy Integration :
- Pure RTL without hidden CPU or software components.
- Vendor agnostics FPGA/ASIC implementation.
Licensing Options
For additional information contact: sales@xiphera.com or visit Xiphera
Documentation
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