Ascon IP core implements a lightweight, sponge-based encryption algorithm, being ideal for constrained environments such as IoT devices. Ascon performs three cryptographic primitives: Authenticated Encryption with Associated Data (AEAD), hashing, and extendable output function (XOF), offering a smaller alternative for e.g. AES-GCM and SHA-3 IP cores.
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Features and Benefits
- Optimized Resource Requirements:
- Approximately 5000 4-input Lookup Tables (4LUTs) on a typical Microchip® FPGA implementation.
- High throughput, up to 50 Gbps on ChaCha20-Poly 1305.
- Versatile Algorithm:
- Supports ASCON-128/128a/80pq/Hash/Hasha as well as XOF and XOFa.
- Secure Architecture:
- The execution time is independent of the input values and, consequently, provides full protection against timing-based side-channel attacks.
- Standard Compliance:
- Compliant with Ascon specification 1.2 (31.05.2021) which is the version that was selected to be standardized by NIST.
- Easy Integration:
- The 64-bit interface supports easy integration to various system.
- Pure RTL without hidden CPU or software components.
- Vendor agnostic FPGA/ASIC implementation.
Licensing Options
For additional information contact: sales@xiphera.com or visit Xiphera
Documentation
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