Xiphera's extreme speed MACSEC IP core implements the MACsec protocol as standardized in IEEE Std 802.1AE-2018. The MACsec protocol defines a security infrastrucure for Layer 2 (as per the OSI model) traffic by assuring that a received frame has been sent by a transmitting station that claimed to send it. Furthermore, the traffic between stations is both encrypted to provide data confidentiality and authenticated to provide data integrity.
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Features and Benefits
- Optimized resource requirements:
- Does not require any multipliers, DSPBlocks or internal memory in a typical Microchip® FPGA implementation.
- Performance:
- Achieves a high throughput up to 100s of Gbps compliant with NIST Standards.
- The key, initialization vector (IV), and the mode of operation can be dynamically updated for every 128-bit data clock.
- Standard Compliance:
- Fully compliant with MACsec protocol as standardized in IEEE Std 802.1AE-2018.
- The cipher suite (GCM-AES-256 or GCM-AES-XPN-256) is fully compliant with the Advanced Encryption Algorithm (AES) standard, as well as with the Galois Counter Mode (GCM) standard.
- Passes the relevant test vectors specified in Annex C of IEEE Std 802.1AE-2018
- Easy Integration :
- Pure RTL without hidden CPU or software components.
- Vendor agnostics FPGA/ASIC implementation.
Licensing Options
For additional information contact: sales@xiphera.com or visit Xiphera
Documentation
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