To transfer data over non-zero endpoint, user just needs to manage this FIFO interface. User can write down VHDL, Verilog or System Verilog code to manage this FIFO interface. In this IP core, processor is responsible to manage transfer for endpoint 0 (default control endpoint). IP core has AXI4 interface by which processor can communicate with IP core. This provides flexibility to the user to manage enumeration data.
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Features and Benefits
- Supports LS (1.5 Mbps), FS (12 Mbps) and HS (480 Mbps) modes.
- Supports Control, Bulk, Interrupt and Isochronous transfers.
- Capable to support up to 31 endpoints (1 default control endpoint +15 IN/OUT endpoints).
- Supports Test modes (Test J, Test K, Test SE0 NAK, Test Packet).
- Ready to use component.
Licensing Options
For additional information, visit SLS webpage or contact SLS through info@slscorp.com email.
Documentation
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| usb2-0_software_enumeration_fifo_interface | Link |