SLVS-EC Receiver

Scalable Low-Voltage Signaling with Embedded Clock (SLVS-EC™) is Sony's high-speed interface for nextgeneration high-resolution Complementary Metal-Oxide-Semiconductor (CMOS) image sensors. This standard is tolerant of lane-to-lane skew because of embedded clock technology. It makes a board-level design easy in terms of high-speed and long-distance transmission. SLVS-EC Rx IP core provides SLVS-EC interface for PolarFire® FPGA to receive image sensor data. The IP supports speed up to 9.504 Gbps. The IP core supports two, four, and eight lanes for RAW-8, RAW-10, RAW-12, and RAW-16 configurations. PolarFire transceiver is used as the PHY interface for the SLVS-EC sensor since the SLVS-EC interface uses embedded clock technology. It also uses 8b10b encoding, which can be recovered using the PolarFire transceiver. PolarFire FPGA has up to 24 low-power 12.7 Gbps transceiver lanes. These transceiver lanes can be configured as the SLVS-EC PHY receiver lanes. As shown in the preceding figure, the transceiver outputs are connected to SLVS-EC Rx IP core.