TCP/IP Full Accelerator for 10G/25G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width, pipelined all-RTL implementation for ultra low Latency. This IP Core can accelerate CPUs by offloading TCP/UDP/IP processing into programmable logic (“Offloading”), bring full TCP/UDP/IP connectivity to FPGAs even if no CPU available (“Full Acceleration”).
Log in to myMicrochip to access tools and benefits. Sign up in just one minute.
Maximize Your Experience: Reap the Personalized Advantages by Completing Your Profile to Its Fullest! Update Here
Stay in the loop with the latest from Microchip! Update your profile while you are at it. Update Here
Complete your profile to access more resources.Update Here!
true
Features and Benefits
- High-Performance Network Processing:
- Synthesizable HDL implementation enabling full line rate operation (70+ Gbps FPGA, 100+ Gbps ASIC).
- Scalable Throughput:
- 128-bit bi-directional data paths with streaming interfaces for maximum bandwidth.
- Multiple TCP Engines:
- Multiple parallel engines for efficient and scalable concurrent connections.
- Integrated NIC Functionality:
- Optional Network Interface Card features, including bypass capability.
- Flexible Interface Options:
Licensing Options
For more information, contact sales-web@missinglinkelectronics.com or visit https://www.missinglinkelectronics.com/
Documentation
|
Title
|
||
|---|---|---|
| mle_npap | Link |