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MIV_RV32IMAF_L1_AHB

The MIV_RV32IMAF_L1_AHB is a softcore processor designed to implement the RISC-V instruction setfor use in Microsemi FPGAs. The processor is based on Rocket-Chip, which contains a highperformancesingle-issue in order execution pipeline 32-bit RISC-V core.


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Features and Benefits

  • Designed for low power ASIC microcontroller and FPGA soft-core implementations.
  • Integrated 8Kbytes instructions cache and 8Kbytes data cache.
  • A Platform-Level Interrupt Controller (PLIC) supports up to 31 programmable interrupts with a singlepriority level 0. The 31 interrupt inputs are serviced from 0 to 31 in ascending order.
  • Supports the RISC-V standard RV32IMAF ISA.
  • On-Chip debug unit with a JTAG interface.
  • Two external AHB interfaces for IO and memory.
  • Support for Error-Correcting Code (ECC) cache on RTG4 and PolarFire.

    • Licensing Options

    Free with any Libero License

    Documentation

    Title
    MiV_RV32IMAF_L1_AHB_HB.pdf Download