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CORECORTEXM1


CORECORTEXM1 has a three-stage pipelineand runs the ARMv6-M instruction set; it is essentially a functional subset of the Cortex-M3 processor. The streamlined CORECORTEXM1, developed for use in embedded applications, is designed to balance size and speed when implemented in an FPGA.

Download CORECORTEXM1 version 4.1 cpz file from the documentation section below, to work with PolarFire® and RTG4™ FPGA families.


Features and Benefits


  • 32-bit RISC architecture (Armv6-M)
  • 32-bit AHB-Lite bus interface
  • Three-stage pipeline
  • 32-bit ALU
  • 4-GB memory addressing range (the upper 0.5 GB is reserved)
  • Real-time debug
  • JTAG interface
  • TCM hardware enable/disable (from user GUI)

Documentation


Title
CoreCortexM1 User Guide Download
CoreCortexM1_v4.1.100.zip Download