CoreReset_PF allows synchronization of the resets to the user-specified clock domain to which each reset CoreReset_PF allows synchronization of the resets to the user-specified clock domain to which each reset is feeded, so that, when assertion is asynchronous, negation is synchronous to the clock.
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Features and Benefits
- Generates a reset, which is asserted asynchronously by one of multiple potential sources and which negates synchronously to a specified clock. This ensures that the recovery time of downstream logic is met and that all flip flops come out of reset in the same clock period.
- Multiple resets can be used such as external gpio, phase lock loop lock or init done in conjunction with the master reset from the system controller (through CORESYSSERVICES_PF).
Licensing Options
Free with any Libero License
Documentation
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| CoreReset_PF_HB.pdf | Download |