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CorePCIe_AHBLtoAXI

he CorePCIe_AHBLtoAXI IP core provides an interface (bridge) between the AHBL domain and AXIdomain. The IP core is an AHBL slave and an AXI master. The core allows an AHBL bus system to beconnected to an AXI bus enabling an AHBL master to communicate with an AXI slave.


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Features and Benefits

  • AHBL and AXI domains are synchronous (common clock for both AHBL and AXI)
  • Generates only single-beat increment burst AXI transactions
  • Converts 32-bit AHBL write/read transactions into 64-bit AXI write/read transactions, respectively

    • Licensing Options

    Free with any Libero License

    Documentation

    Title
    CorePCIe_AHBLtoAXI_HB.pdf Download