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COREBOOTSTRAP

CoreBootStrap connects as a master to a 32-bit AHB bus on which an on-chip RAM block, that can also be accessed by the processor resides


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Features and Benefits

  • Provides bootstrap capability for a processor sharing an AHB bus, whereby boot code is extracted from SPI and placed in AHB-based RAM for fast execution after exiting the reset state
  • Supports all available SPI Flash chips, through Motorola Mode 0 signaling, and parameterized software reset command sequences along with various timing parameters to handle differences between SPI chip manufacturers
  • Three and four byte addressing options parameterized to handle SPI flash chips of different sizes
  • Supports three reset sources:o Power-on reseto External reseto Processor reset
  • Resets extended to parameterized durations:o Power-on reset length to overcome SPI Flash chip?s widely-varying specifications from power-up to device available, which can range from under 200us to over 5mso Default reset duration parameterized separately to cover the other two reset sources

    • Licensing Options

    Free with any Libero License

    Documentation

    Title
    CoreBootStrap_HB.pdf Download