The CoreAXI4SRAM provides access to the embedded large SRAM (LSRAM) and small SRAM (uSRAM) blocks available on the PolarFire system-on-chip (SoC) field programmable gate array (FPGA) family device.
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Features and Benefits
- Supports AXI4 protocol only
- Supports 1:1 synchronous clock
- Interface data widths: 32 and 64-bits
- Supports AXI4 increment and wrap transfers, except fixed transfers
- Configurable Read / Write, Read-only or Write-only interfaces
Licensing Options
Free with any Libero License
Documentation
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| HB0716: CoreAXI4SRAM v2.1 Handbook | Download |