The Microchip FPGA Core10GBaseKR_PHY core is designed in accordance with the IEEE® 802.3 2012 standard and supports Core10GBaseKR_PHY interface for the Backplane operations. This configurable core provides the Physical (PHY) layer when used with a transceiver interface. This IP interfaces with the Ten Gigabit Media Independent Interface (XGMII) compliant Media Access Control (MAC) at the system side and the transceiver block at the Line side. The physical layer is designed to work seamlessly with the PolarFire® and PolarFire® SoC transceiver using the Physical Medium Attachment (PMA) mode.
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Features and Benefits
- 64-bit XGMII interface towards the MAC side and 32-bit PMA interface
- Programmable IEEE Clause 73 (Auto-Negotiation) and Clause 72 (Link Training)
- APB interface for the register access
- 64B/66B Physical Coding Sublayer (PCS) encoding or decoding as per the IEEE Clause 49
- Elastic Buffer implemented in the Receive path to absorb the +/-100 ppm frequency variation. This is achieved by addition or deletion of the skip characters in the Ethernet traffic.
- FEC capability as per the IEEE 802.3-2012 specification
Documentation
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| Core10GBaseKR_PHY User Guide | Download |