Description: SmartDebug is a FPGA fabric-based and memory content debugging tool for the PolarFire, PolarFire® SoC, IGLOO® 2,  SmartFusion® 2 and RTG4™ FPGA families. In this video, we will also present Memory Log Analyzer which is a GUI-based tool that analyzes the debug log generated while DDR memory initialization and training are carried out by the software running on the FPGA Core Complex. Links: https://www.microchip.com/en-us/products/fpgas-and-plds/fpgas/polarfire-fpgas https://www.microchip.com/en-us/products/fpgas-and-plds/fpgas/igloo-2-fpgas https://www.microchip.com/en-us/products/fpgas-and-plds/system-on-chip-fpgas/smartfusion-2-fpgas Memory Log Analyzer software download link: https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/SOCDesignFiles/Memory_Log_Analyzer_GUI_Installer.zip Memory Log Analyzer Help Online Documentation link: https://onlinedocs.microchip.com/oxy/GUID-7F276F66-9418-456E-9FA3-8E7EE40C9E25-en-US-7/GUID-174402C0-E316-4BF8-BA7F-28E312E9049D.html Downloaded the example source files from the DDR Demo on PolarFireSoC (mpfs-hal-ddr-demo) GitHub repository: https://github.com/polarfire-soc/polarfire-soc-bare-metal-examples