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Space Rated FPGA - In Flight Reprogramming

Part Number: FpgaInFlightReprog-TSS

Summary:

In the frame of a Space flight application deployment,system partial or full reconfiguration/reprogramming after integration is becoming a stringent requirements. It can allow late bug fixes in a system in the last stages of development and also after launch of the mission. You can also take the benefits of the reprogramming capability for Processing algorithm enhancement/fine tuning after

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6/1/2020
12MB

Application Notes

Product Features

    Demonstration 1 : RTG4 Reconfiguration with SAMRH71F20

    The demonstration of the RTG4 reconfiguration relies on a basic setup built around the commercially of-the-shelves development kit of the RTG4 FPGA and of the SAMRH71F20 microcontroler.
    The RTG4 DEV KIT and the SAMRH71F20-EK are basically interconnected through a set of 7 IOs
    The SAMRH71F20 embeds the DirectC library that supports embedded in-system programming for a variety of Microsemi FPGAs, including RTG4
    To emulate the storage of the bistream received from the telemetry interface, the demonstration relies on a SD memory card plugged to the IO expansion connector of the SAMRH71F20 board.

    Full details on how to interconnect the two boards and run the demo application at : https://github.com/MicrochipTech/adg_fpga_reconfiguration

    Demonstration 2 : RT-PolarFire Reconfiguration with SAMRH71F20

    The demonstration of the RTG4 reconfiguration relies on a basic setup built around the commercially of-the-shelves development kit of the PolarFire DEV KIT FPGA and of the SAMRH71F20 microcontroler.
    The PolarFire DEV KIT and the SAMRH71F20-EK are basically interconnected through a set of 7 IOs
    The SAMRH71F20 embeds the DirectC library that supports embedded in-system programming for a variety of Microsemi FPGAs, including RTG4
    To emulate the storage of the bistream received from the telemetry interface, the demonstration relies on a SD memory card plugged to the IO expansion connector of the SAMRH71F20 board.

    Full details on how to interconnect the two boards and run the demo application at : https://github.com/MicrochipTech/adg_fpga_reconfiguration

Summary

In the frame of a Space flight application deployment,system partial or full reconfiguration/reprogramming after integration is becoming a stringent requirements. It can allow late bug fixes in a system in the last stages of development and also after launch of the mission. You can also take the benefits of the reprogramming capability for Processing algorithm enhancement/fine tuning after mission deployment and for re-purposing of functioning flight hardware after mission completion. Combining the flexibility of the radiation tolerant FPGA structure and the efficiency of the radiation hardened or radiation tolerant micro-controllers, Microchip can provide Space Applications with the highest level of In-Flight reconfiguration.

With the RTG4 and RT-PolarFire FPGA families, Microchip offers an unrivaled space rated FPGAs portfolio that can be reprogrammed during their flight. Reprogramming of those FPGAs is done thanks to a simple interface that can be managed by a processor/micro-controller. Combined with the SAMRH71F20 Space rated micro-controller that is capable to operate up to 200DMIPS/s, it becomes quite simple to provide a reconfigurable architecture to your Space application. Interconnecting the FPGA and the micro-controller with only a few IOs allows to manage the complete reprogramming process, emulating the JTAG interface and the configuration protocol directly in the micro-controller firmware.

Thanks to the RTG4 and RT-PolarFire FPGAs and the SAMRH71F20, In application reconfiguration is now available for Space flight applications.
Two demonstrations are already available and ready to use, based on standard development kits and Software of-the-shelves.

The main principle of the RT-FPGA reconfiguration is that the micro-controller manages the in-flight programming process of the RT FPGA thanks to the Direct C library that emulates both the JTAG interface of the FPGA and the configuration protocol. The micro-controller manages the up-link via telecommand system to accepts new programming bitstream for the FPGA, stores the bit stream in memory, places FPGA into programming mode, executes Direct C code to initiate transfer of programming bit stream to FPGA, monitors FPGA return to operation and re-initiate programming in case of programming upset.