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ZL30255

Jitter Attenuator

Status: In Production

Features:

  • Three Input Clocks Per Channel
  • Two Independent Channels
  • Any input frequency from 1kHz to 1250MHz (1kHz to 300MHz for CMOS)
  • Automatic or manual reference switching
  • Programmable bandwidth, 14Hz to 500Hz
  • Attenuates jitter up to several UI
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

The ZL30255 is a flexible, high-performance, clock multiplier/jitter attenuator IC. From any input clock frequency 1kHz to 1250MHz this device can produce frequency-locked output frequencies from <1Hz to 1035MHz and as many as 6 differential or 12 CMOS output clock signals. Output jitter is typically 0.16 to 0.28ps RMS (12kHz to 20MHz). Automatic self-configuration from internal EEPROM allows clock signals to be available immediately after power-up or reset.

Additional Features
  • Two Independent Channels
  • Three Input Clocks Per Channel
    • Two Differential/CMOS inputs
    • One single-ended/CMOS input
    • Any input frequency from 1kHz to 1250MHz (1kHz to 300MHz for CMOS)
    • Inputs continually monitored for activity and frequency accuracy
    • Automatic or manual reference switching
  • Low-Bandwidth DPLL Per Channel
    • Programmable bandwidth, 14Hz to 500Hz
    • Attenuates jitter up to several UI
    • Freerun or digital hold on loss of all inputs
    • Digitally controlled phase adjust
  • Low-Jitter Fractional-N APLL and 3 Outputs per Channel
    • Any Output Frequency from <1Hz to 1035MHz
    • High-resolution fractional frequency conversion with 0ppm error
    • Easy-to-configure, encapsulated design requires no external VCXO or loop filter components
    • Each output has independent dividers
    • Output Jitter Typically 0.16 to 0.28ps RMS (12kHz to 20MHz integration band)
    • Outputs are CML or 2xCMOS, can interface to LVDS, LVPECL, HSTL, SSTL and HCSL
    • In 2xCMOS mode, the P and N pins can be different frequencies (e.g. 125MHz and 25MHz)
    • Per-output supply pin with CMOS output voltages from 1.5V to 3.3V
    • Precise output alignment circuitry and per-output phase adjustment
    • Per-output enable/disable and glitchless start/stop (stop high or low)
  • General Features
    • Automatic self-configuration at power-up from internal EEPROM; up to four configurations per channel, pin-selectable
    • Numerically controlled oscillator mode
    • Spread-spectrum modulation mode
    • SPI or I2C processor Interface
    • Tiny 5x10mm LGA package
    • Easy-to-use evaluation software
    • Each channel of the ZL30255 can be ordered with up to four user-defined, factory-programmed device configurations
Parametrics
Name
Value
Type
General Purpose
DPLLs or Paths
2
DPLL Bandwidth (Hz)
14 – 500
Inputs
2 XTAL/SE, 6 D/SE
Diff Outputs
6
CMOS Outputs
12
Low-Jitter Synthesizers
2
Typical Jitter (12kHz-20MHz) fs RMS
160
Diff InputFreq Range
1 kHz–1250 M
Output Freq Range
<1 Hz–1035 M
NV Memory
Int EE
NCO ppb
0.01

Documents

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Data Sheets

  
2208KB

Software Tools

  
5980KB

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RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Dimension
Solder Composition
JEDEC Indicator
RoHS
China EFUP
ZL30255LFF7
0.130900
0.330000
64
VFLGA
5x10x0.9mm
NiAu
e4
ZL30255LFG7
0.130900
0.523810
64
VFLGA
5x10x0.9mm
NiAu
e4
ZL30255LFG7Q00W
0.130900
0.523810
64
VFLGA
5x10x0.9mm
NiAu
e4
ZL30255-LFG7-UA
0.130900
0.523810
64
VFLGA
5x10x0.9mm
NiAu
e4
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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