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SY89873L

Status: In Production

Features:

  • >2.0GHz fMAX output toggle
  • >3.0GHz fMAX input
  • <800ps tPD (matched-delay between banks)
  • <15ps within-device skew
  • <190ps rise/fall time
  • <1psRMS cycle-to-cycle jitter
  • Unique input termination and VTpin for DC-coupled and AC-coupled inputs: any differential inputs (LVPECL, LVDS, CML, HSTL)
  • Precision differential LVDS outputs
  • Matched delay: all outputs have matched delay, independent of divider setting
  • TTL/CMOS inputs for select and reset/disable
  • Bank A: Buffered copy of input clock (undivided)
  • Bank B: Divided output (÷2, ÷4, ÷8, ÷16), two copies
  • 3.3V power supply
  • Wide operating temperature range: -40°C to +85°C
  • Available in 16-pin (3mm x 3mm) QFN package
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

This 3.3V low-skew, low-jitter, precision LVDS output clock divider accepts any high-speed differential clock input (AC- or DC-coupled) CML, LVPECL, HSTL or LVDS and divides down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock. The SY89873L includes two output banks. Bank A is an exact copy of the input clock (pass through) with matched propagation delay to Bank B, the divided output bank. Available divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, 77MHz or 38MHz auxiliary clock components.

The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to all AC- or DC-coupled differential logic standards. A VREF-AC reference is included for AC-coupled applications.The SY89873L is part of Micrel's high-speed Precision Edge® timing and distribution family. For 2.5V applications, consider the SY89872U. For applications that require an LVPECL output, consider the SY89871U.The /RESET input asynchronously resets the divider outputs (Bank B). In the pass-through function (Bank A) the /RESET synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /N). Refer to the Timing Diagram.

Additional Features
    • Guaranteed AC performance
      • >2.0GHz fMAX output toggle
      • >3.0GHz fMAX input
      • <800ps tPD (matched-delay between banks)
      • <15ps within-device skew
      • <190ps rise/fall time
    • Low jitter design
      • <1psRMS cycle-to-cycle jitter
    • Unique input termination and VTpin for DC-coupled and AC-coupled inputs: any differential inputs (LVPECL, LVDS, CML, HSTL)
    • Precision differential LVDS outputs
    • Matched delay: all outputs have matched delay, independent of divider setting
    • TTL/CMOS inputs for select and reset/disable
    • Two LVDS output banks (matched delay)
      • Bank A: Buffered copy of input clock (undivided)
      • Bank B: Divided output (÷2, ÷4, ÷8, ÷16), two copies
    • 3.3V power supply
    • Wide operating temperature range: -40°C to +85°C
    • Available in 16-pin (3mm x 3mm) QFN package
Parametrics
Name
Value
Product Type
Divider
Description
2 Banks (÷1, ÷2, ÷4, ÷8, ÷16); 2 Outputs
Input
ANY
Output
LVDS
Supply Voltage
3.3V
Max Freq (GHz)
2
Max Prop Delay (ps)
800
Icc (mA)
85
Max Within Device Skew (ps)
15
OE
True
RPE
False
FSI
False
Input Mux
False
Input EQ
False
Output Type
LVDS

Documents

Jump to:

Data Sheet

04/30/2018
660KB

User Guides

11/11/2015
134KB

Development tools data is currently unavailable.

RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Width
Solder Composition
JEDEC Indicator
RoHS
China EFUP
SY89873LMG
0.021300
0.050000
16
VQFN
3x3x1.00mm
NiPdAu
e4
SY89873LMG-TR
0.021300
0.801700
16
VQFN
3x3x1.00mm
NiPdAu
e4
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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