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SY89221U

Status: In Production

Features:

  • Four low-skew LVPECL output banks with independently programmable ÷1, ÷2 and ÷4 divider options
  • Four output banks, 15 total outputs
  • Accepts a clock frequency up to 1.5GHz
  • <1600ps IN-to-OUT propagation delay
  • <270ps rise/fall time
  • <35ps within-bank skew
  • Fail Safe Input
  • Prevents outputs from oscillating
  • <1psRMS random jitter
  • <10psPP total jitter (clock)
  • Patent-pending input termination and VT pin accepts DC- and AC-coupled inputs (CML, PECL, LVDS)
  • CMOS/TTL-compatible output enable (EN) and divider select control
  • 2.5V ±5% or 3.3V ±10% power supply
  • -40°C to +85°C temperature range
  • Available in 64-pin TQFP
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

The SY89221U is a 2.5/3.3V precision, high-speed, integrated clock divider and LVPECL fanout buffer capable of handling clocks up to 1.5GHz. Optimized for communications applications, the four independently controlled output banks are phasematched and can be configured for pass through ÷1, ÷2 or ÷4 divider ratios.The differential input includes Micrel's unique, 3-pin input termination architecture that allows the user to interface to any differential signal (AC- or DC-coupled) as small as 100mV (200mVPP) without any level shifting or termination resistor networks in the signal path. The low-skew, low-jitter outputs are LVPECL compatible with extremely fast rise/fall times that are guaranteed to be less than 220ps.The /MR (master reset) input asynchronously resets the outputs. A four-clock delay after de-asserting /MR allows the counters to synchronize and start the outputs from the same state without any runt pulse.The SY89221U is part of Micrel's Precision Edge® product family.

Additional Features
    • Four low-skew LVPECL output banks with independently programmable ÷1, ÷2 and ÷4 divider options
    • Four output banks, 15 total outputs
    • Guaranteed AC performance over temperature and voltage:
      • Accepts a clock frequency up to 1.5GHz
      • <1600ps IN-to-OUT propagation delay
      • <270ps rise/fall time
      • <35ps within-bank skew
    • Fail Safe Input
      • Prevents outputs from oscillating
    • Ultra-low jitter design:
      • <1psRMS random jitter
      • <10psPP total jitter (clock)
    • Patent-pending input termination and VT pin accepts DC- and AC-coupled inputs (CML, PECL, LVDS)
    • CMOS/TTL-compatible output enable (EN) and divider select control
    • 2.5V ±5% or 3.3V ±10% power supply
    • -40°C to +85°C temperature range
    • Available in 64-pin TQFP
Parametrics
Name
Value
Product Type
Divider
Description
4 Banks (÷1, ÷2, ÷4); 15 Outputs
Input
ANY
Output
LVPECL
Supply Voltage
2.5/3.3V
Max Freq (GHz)
1.5
Max Prop Delay (ps)
1600
Icc (mA)
140
Max Within Device Skew (ps)
35
OE
False
RPE
False
FSI
True
Input Mux
True
Input EQ
False
Output Type
LVPECL

Documents

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Data Sheet

12/04/2018
841KB

User Guides


Development tools data is currently unavailable.

RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Width
Solder Composition
JEDEC Indicator
RoHS
China EFUP
SY89221UHY
0.261300
1.607500
64
TQFP
10x10x1.0mm
Matte Tin
e3
SY89221UHY-TR
0.261300
0.904600
64
TQFP
10x10x1.0mm
Matte Tin
e3
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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