The SPMI-CTRL core implements a highly featured, easy-to-use controller for the MIPI System Power Management Interface (MIPI-SPMI) bus. It supports the latest version (v2.0) of the MIPI-SPMI specification, and is suitable for the implementation of either master or slave nodes in an SPMI bus.
Log in to myMicrochip to access tools and benefits. Sign up in just one minute.
Maximize Your Experience: Reap the Personalized Advantages by Completing Your Profile to Its Fullest. Update Here
Stay in the loop with the latest from Microchip. Update your profile while you are at it. Update Here
Complete your profile to access more resources. Update Here
true
Features and Benefits
- MIPI-SPMI v2.0 Master or Slave
- Supports High Speed (HS) and Low Speed (LS) device classes, all commands and arbitration levels.
- Low Host Processor Overhead
- Directly bridges SPMI and AHB bus address space, allowing SPMI address space mapping to either a shared memory or directly to peripheral registers
Licensing Options
For additional information, contact info@cast-inc.com or visit CAST
Documentation
|
Title
|
||
|---|---|---|
| spmi--mipi-spmi-master-or-slave-controller | Link |